From patchwork Thu Jul 2 07:47:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 11638043 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2AF0F6C1 for ; Thu, 2 Jul 2020 07:48:23 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0763320899 for ; Thu, 2 Jul 2020 07:48:23 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=baylibre-com.20150623.gappssmtp.com header.i=@baylibre-com.20150623.gappssmtp.com header.b="LNV/MQa4" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 0763320899 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 98A616EA82; Thu, 2 Jul 2020 07:48:14 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-wr1-x444.google.com (mail-wr1-x444.google.com [IPv6:2a00:1450:4864:20::444]) by gabe.freedesktop.org (Postfix) with ESMTPS id D2CB16EA82 for ; Thu, 2 Jul 2020 07:48:13 +0000 (UTC) Received: by mail-wr1-x444.google.com with SMTP id j4so24505838wrp.10 for ; Thu, 02 Jul 2020 00:48:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ci6ooCorfZ5Pyg0EKRJeiIb8tL4fvaY6SA1psV8+SCw=; b=LNV/MQa46fdkURV0u2B9ejwweqqRpDIKhbBKeEfqQcMmNjWyXRBajz9QDNiMKyTvHH 6gCtxD86tRUjjW+s8TPUXvkvbr+OS3YJmDP/gHeMhNhQUmSotRgCSjKufKXvQIm+mMGf 45WlajdJ8HA6WbJTPr2ybTp+4kuKLodRk1M/Ar2ySwtoMijjG6DrZpV971+ZQCP9GqK6 M0q1v08l3I0mYN0A8eztbGf+XZMi5Sa2tEkkVPvse1xndXRvpU6iaFzInjnZzLffMk11 uEjN4Oak4gG/6Zqt1H3TdkYAy8G5ytuYlu5nFtvT3XxVgT04P+bg9smB4+ak9LRY40GG IkHw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ci6ooCorfZ5Pyg0EKRJeiIb8tL4fvaY6SA1psV8+SCw=; b=KvvLb/cn/rYVsG3fPspSb34jIXGFX47MQxjLLdf5sRYAJDFuRzqcpZ4axsA/UXD0dp gP43rCmIUFt9issHgohDmPzXW8hMvlHJFmmyY1zHzDhUL4aqCn8MMmU7iaZkpE5lKs/N aLUh1GNDE06glNjBJtRtImxanNXSOjcNbX6P+jrHJggUAwbIOuo6P/azAj2NvdVGofTQ eFhMcAx0ZUg7IhqEH91fyuVhmpj11XSb5QcvFhYjX8aDQQCrfG01fLFY8f3tIHu9YiO9 p6IJirsZNL0llS7f4yftEE2nP5F3LFu6X18zKZr5q944jqWVv8vsw6Psyn68gcCa/CF0 Ov7g== X-Gm-Message-State: AOAM531GB89dh6c5po3x7tKaShv+Uwp8AxvQkz87EE3EuTxLaiBuFHGH vUg5j5iEDK2+0XuA8f/qvQ9KUQ== X-Google-Smtp-Source: ABdhPJzRyKGfdgm9MhttaHg18K3kT7W+KjIdtWl18Cnj7zu3qrmOSvKfv2O+bPsm4/+MxHKkrvWfIA== X-Received: by 2002:a5d:4687:: with SMTP id u7mr31938378wrq.357.1593676092277; Thu, 02 Jul 2020 00:48:12 -0700 (PDT) Received: from bender.baylibre.local ([2a01:e35:2ec0:82b0:7023:727a:c688:cf9b]) by smtp.gmail.com with ESMTPSA id z1sm10001882wru.30.2020.07.02.00.48.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jul 2020 00:48:11 -0700 (PDT) From: Neil Armstrong To: daniel@ffwll.ch, dri-devel@lists.freedesktop.org Subject: [PATCH v8 6/6] drm/meson: crtc: handle commit of Amlogic FBC frames Date: Thu, 2 Jul 2020 09:47:59 +0200 Message-Id: <20200702074759.32356-7-narmstrong@baylibre.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20200702074759.32356-1-narmstrong@baylibre.com> References: <20200702074759.32356-1-narmstrong@baylibre.com> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jianxin.pan@amlogic.com, Neil Armstrong , Kevin Hilman , linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Since the VD1 Amlogic FBC decoder is now configured by the overlay driver, commit the right registers to decode the Amlogic FBC frame. Tested-by: Kevin Hilman Signed-off-by: Neil Armstrong --- drivers/gpu/drm/meson/meson_crtc.c | 118 +++++++++++++++++++++-------- 1 file changed, 88 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/meson/meson_crtc.c b/drivers/gpu/drm/meson/meson_crtc.c index e66b6271ff58..2854272dc2d9 100644 --- a/drivers/gpu/drm/meson/meson_crtc.c +++ b/drivers/gpu/drm/meson/meson_crtc.c @@ -291,6 +291,10 @@ static void meson_crtc_enable_vd1(struct meson_drm *priv) VPP_VD1_PREBLEND | VPP_VD1_POSTBLEND | VPP_COLOR_MNG_ENABLE, priv->io_base + _REG(VPP_MISC)); + + writel_bits_relaxed(VIU_CTRL0_AFBC_TO_VD1, + priv->viu.vd1_afbc ? VIU_CTRL0_AFBC_TO_VD1 : 0, + priv->io_base + _REG(VIU_MISC_CTRL0)); } static void meson_g12a_crtc_enable_vd1(struct meson_drm *priv) @@ -300,6 +304,10 @@ static void meson_g12a_crtc_enable_vd1(struct meson_drm *priv) VD_BLEND_POSTBLD_SRC_VD1 | VD_BLEND_POSTBLD_PREMULT_EN, priv->io_base + _REG(VD1_BLEND_SRC_CTRL)); + + writel_relaxed(priv->viu.vd1_afbc ? + (VD1_AXI_SEL_AFBC | AFBC_VD1_SEL) : 0, + priv->io_base + _REG(VD1_AFBCD0_MISC_CTRL)); } void meson_crtc_irq(struct meson_drm *priv) @@ -383,36 +391,86 @@ void meson_crtc_irq(struct meson_drm *priv) /* Update the VD1 registers */ if (priv->viu.vd1_enabled && priv->viu.vd1_commit) { - switch (priv->viu.vd1_planes) { - case 3: - meson_canvas_config(priv->canvas, - priv->canvas_id_vd1_2, - priv->viu.vd1_addr2, - priv->viu.vd1_stride2, - priv->viu.vd1_height2, - MESON_CANVAS_WRAP_NONE, - MESON_CANVAS_BLKMODE_LINEAR, - MESON_CANVAS_ENDIAN_SWAP64); - /* fallthrough */ - case 2: - meson_canvas_config(priv->canvas, - priv->canvas_id_vd1_1, - priv->viu.vd1_addr1, - priv->viu.vd1_stride1, - priv->viu.vd1_height1, - MESON_CANVAS_WRAP_NONE, - MESON_CANVAS_BLKMODE_LINEAR, - MESON_CANVAS_ENDIAN_SWAP64); - /* fallthrough */ - case 1: - meson_canvas_config(priv->canvas, - priv->canvas_id_vd1_0, - priv->viu.vd1_addr0, - priv->viu.vd1_stride0, - priv->viu.vd1_height0, - MESON_CANVAS_WRAP_NONE, - MESON_CANVAS_BLKMODE_LINEAR, - MESON_CANVAS_ENDIAN_SWAP64); + if (priv->viu.vd1_afbc) { + writel_relaxed(priv->viu.vd1_afbc_head_addr, + priv->io_base + + _REG(AFBC_HEAD_BADDR)); + writel_relaxed(priv->viu.vd1_afbc_body_addr, + priv->io_base + + _REG(AFBC_BODY_BADDR)); + writel_relaxed(priv->viu.vd1_afbc_en, + priv->io_base + + _REG(AFBC_ENABLE)); + writel_relaxed(priv->viu.vd1_afbc_mode, + priv->io_base + + _REG(AFBC_MODE)); + writel_relaxed(priv->viu.vd1_afbc_size_in, + priv->io_base + + _REG(AFBC_SIZE_IN)); + writel_relaxed(priv->viu.vd1_afbc_dec_def_color, + priv->io_base + + _REG(AFBC_DEC_DEF_COLOR)); + writel_relaxed(priv->viu.vd1_afbc_conv_ctrl, + priv->io_base + + _REG(AFBC_CONV_CTRL)); + writel_relaxed(priv->viu.vd1_afbc_size_out, + priv->io_base + + _REG(AFBC_SIZE_OUT)); + writel_relaxed(priv->viu.vd1_afbc_vd_cfmt_ctrl, + priv->io_base + + _REG(AFBC_VD_CFMT_CTRL)); + writel_relaxed(priv->viu.vd1_afbc_vd_cfmt_w, + priv->io_base + + _REG(AFBC_VD_CFMT_W)); + writel_relaxed(priv->viu.vd1_afbc_mif_hor_scope, + priv->io_base + + _REG(AFBC_MIF_HOR_SCOPE)); + writel_relaxed(priv->viu.vd1_afbc_mif_ver_scope, + priv->io_base + + _REG(AFBC_MIF_VER_SCOPE)); + writel_relaxed(priv->viu.vd1_afbc_pixel_hor_scope, + priv->io_base+ + _REG(AFBC_PIXEL_HOR_SCOPE)); + writel_relaxed(priv->viu.vd1_afbc_pixel_ver_scope, + priv->io_base + + _REG(AFBC_PIXEL_VER_SCOPE)); + writel_relaxed(priv->viu.vd1_afbc_vd_cfmt_h, + priv->io_base + + _REG(AFBC_VD_CFMT_H)); + } else { + switch (priv->viu.vd1_planes) { + case 3: + meson_canvas_config(priv->canvas, + priv->canvas_id_vd1_2, + priv->viu.vd1_addr2, + priv->viu.vd1_stride2, + priv->viu.vd1_height2, + MESON_CANVAS_WRAP_NONE, + MESON_CANVAS_BLKMODE_LINEAR, + MESON_CANVAS_ENDIAN_SWAP64); + fallthrough; + case 2: + meson_canvas_config(priv->canvas, + priv->canvas_id_vd1_1, + priv->viu.vd1_addr1, + priv->viu.vd1_stride1, + priv->viu.vd1_height1, + MESON_CANVAS_WRAP_NONE, + MESON_CANVAS_BLKMODE_LINEAR, + MESON_CANVAS_ENDIAN_SWAP64); + fallthrough; + case 1: + meson_canvas_config(priv->canvas, + priv->canvas_id_vd1_0, + priv->viu.vd1_addr0, + priv->viu.vd1_stride0, + priv->viu.vd1_height0, + MESON_CANVAS_WRAP_NONE, + MESON_CANVAS_BLKMODE_LINEAR, + MESON_CANVAS_ENDIAN_SWAP64); + } + + writel_relaxed(0, priv->io_base + _REG(AFBC_ENABLE)); } writel_relaxed(priv->viu.vd1_if0_gen_reg,