| Message ID | CAFXsbZrVZjiyO_G6z6T82t0xT36Zi2gGo0kPnt6n58R-rO3TVg@mail.gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | ARM64: dts: update MDIO speed and preamble for zii-ultra device | expand |
Hi Chris, The subject pattern used for ARM64 i.MX patches is like: arm64: dts: zii-ultra: update MDIO speed and preamble On Sat, Jul 4, 2020 at 10:26 PM Chris Healy <cphealy@gmail.com> wrote: > > Update MDIO configuration with zii-ultra device to fully utilize > MDIO endpoint capabilities. Device supports 12.5MHz clock and > doesn't require MDIO preamble. > > Signed-off-by: Chris Healy <cphealy@gmail.com> Other than that: Reviewed-by: Fabio Estevam <festevam@gmail.com>
Hi Chris, On 7/4/2020 6:26 PM, Chris Healy wrote: > Update MDIO configuration with zii-ultra device to fully utilize > MDIO endpoint capabilities. Device supports 12.5MHz clock and > doesn't require MDIO preamble. > > Signed-off-by: Chris Healy <cphealy@gmail.com> > --- > arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi > b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi > index 6a55165bd76a..98aa67a4c040 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi > @@ -132,6 +132,8 @@ > #address-cells = <1>; > #size-cells = <0>; > status = "okay"; > + suppress-preamble = <1>; suppress-preamble is defined as a boolean, so you can remove the "= <1>" part entirely.
On Tue, Jul 7, 2020 at 2:59 PM Florian Fainelli <f.fainelli@gmail.com> wrote: > > Hi Chris, > > On 7/4/2020 6:26 PM, Chris Healy wrote: > > Update MDIO configuration with zii-ultra device to fully utilize > > MDIO endpoint capabilities. Device supports 12.5MHz clock and > > doesn't require MDIO preamble. > > > > Signed-off-by: Chris Healy <cphealy@gmail.com> > > --- > > arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi | 2 ++ > > 1 file changed, 2 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi > > b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi > > index 6a55165bd76a..98aa67a4c040 100644 > > --- a/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi > > +++ b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi > > @@ -132,6 +132,8 @@ > > #address-cells = <1>; > > #size-cells = <0>; > > status = "okay"; > > + suppress-preamble = <1>; > > suppress-preamble is defined as a boolean, so you can remove the "= <1>" > part entirely. Good point, I'll make the necessary change. > -- > Florian
On Tue, Jul 7, 2020 at 2:54 PM Fabio Estevam <festevam@gmail.com> wrote: > > Hi Chris, > > The subject pattern used for ARM64 i.MX patches is like: > > arm64: dts: zii-ultra: update MDIO speed and preamble Thanks for pointing this out. I have to make a change to this patch anyway so I will resubmit with the correct subject pattern. > > On Sat, Jul 4, 2020 at 10:26 PM Chris Healy <cphealy@gmail.com> wrote: > > > > Update MDIO configuration with zii-ultra device to fully utilize > > MDIO endpoint capabilities. Device supports 12.5MHz clock and > > doesn't require MDIO preamble. > > > > Signed-off-by: Chris Healy <cphealy@gmail.com> > > Other than that: > > Reviewed-by: Fabio Estevam <festevam@gmail.com>
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi index 6a55165bd76a..98aa67a4c040 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi @@ -132,6 +132,8 @@ #address-cells = <1>; #size-cells = <0>; status = "okay"; + suppress-preamble = <1>; + clock-frequency = <12500000>; switch: switch@0 { compatible = "marvell,mv88e6085";
Update MDIO configuration with zii-ultra device to fully utilize MDIO endpoint capabilities. Device supports 12.5MHz clock and doesn't require MDIO preamble. Signed-off-by: Chris Healy <cphealy@gmail.com> --- arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi | 2 ++ 1 file changed, 2 insertions(+)