diff mbox series

[v2,2/4] x86/cpufeatures: Enumerate TSX suspend load address tracking instructions

Message ID 1594088183-7187-3-git-send-email-cathy.zhang@intel.com (mailing list archive)
State New, archived
Headers show
Series Expose new features for intel processor | expand

Commit Message

Zhang, Cathy July 7, 2020, 2:16 a.m. UTC 
Intel TSX suspend load tracking instructions aim to give a way to
choose which memory accesses do not need to be tracked in the TSX
read set. Add TSX suspend load tracking CPUID feature flag TSXLDTRK
for enumeration.

A processor supports Intel TSX suspend load address tracking if
CPUID.0x07.0x0:EDX[16] is present. Two instructions XSUSLDTRK, XRESLDTRK
are available when this feature is present.

The CPU feature flag is shown as "tsxldtrk" in /proc/cpuinfo.

Detailed information on the instructions and CPUID feature flag TSXLDTRK
can be found in the latest Intel Architecture Instruction Set Extensions
and Future Features Programming Reference and Intel 64 and IA-32
Architectures Software Developer's Manual.

Signed-off-by: Kyung Min Park <kyung.min.park@intel.com>
Signed-off-by: Cathy Zhang <cathy.zhang@intel.com>
---
 arch/x86/include/asm/cpufeatures.h | 1 +
 1 file changed, 1 insertion(+)

Comments

Kyung Min Park July 7, 2020, 2:36 a.m. UTC | #1 
Hi Cathy,

On Tue, 2020-07-07 at 10:16 +0800, Cathy Zhang wrote:
> Intel TSX suspend load tracking instructions aim to give a way to
> choose which memory accesses do not need to be tracked in the TSX
> read set. Add TSX suspend load tracking CPUID feature flag TSXLDTRK
> for enumeration.
> 
> A processor supports Intel TSX suspend load address tracking if
> CPUID.0x07.0x0:EDX[16] is present. Two instructions XSUSLDTRK,
> XRESLDTRK
> are available when this feature is present.
> 
> The CPU feature flag is shown as "tsxldtrk" in /proc/cpuinfo.
> 
> Detailed information on the instructions and CPUID feature flag
> TSXLDTRK
> can be found in the latest Intel Architecture Instruction Set
> Extensions
> and Future Features Programming Reference and Intel 64 and IA-32
> Architectures Software Developer's Manual.
> 
> Signed-off-by: Kyung Min Park <kyung.min.park@intel.com>
> Signed-off-by: Cathy Zhang <cathy.zhang@intel.com>
> ---
>  arch/x86/include/asm/cpufeatures.h | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/x86/include/asm/cpufeatures.h
> b/arch/x86/include/asm/cpufeatures.h
> index adf45cf..34b66d7 100644
> --- a/arch/x86/include/asm/cpufeatures.h
> +++ b/arch/x86/include/asm/cpufeatures.h
> @@ -366,6 +366,7 @@
>  #define X86_FEATURE_MD_CLEAR		(18*32+10) /* VERW clears CPU
> buffers */
>  #define X86_FEATURE_TSX_FORCE_ABORT	(18*32+13) /* ""
> TSX_FORCE_ABORT */
>  #define X86_FEATURE_SERIALIZE		(18*32+14) /* SERIALIZE
> instruction */
> +#define X86_FEATURE_TSX_LDTRK           (18*32+16) /* TSX Suspend
> Load Address Tracking */

Since you are using the flag name to "TSX_LDTRK", the commit message
needs to be changed accordingly. The commit message is saying
"tsxldtrk", not "tsx_ldtrk".

>  #define X86_FEATURE_PCONFIG		(18*32+18) /* Intel PCONFIG */
>  #define X86_FEATURE_SPEC_CTRL		(18*32+26) /* ""
> Speculation Control (IBRS + IBPB) */
>  #define X86_FEATURE_INTEL_STIBP		(18*32+27) /* "" Single
> Thread Indirect Branch Predictors */
Greg Kroah-Hartman July 7, 2020, 9:40 a.m. UTC | #2 
On Tue, Jul 07, 2020 at 10:16:21AM +0800, Cathy Zhang wrote:
> Intel TSX suspend load tracking instructions aim to give a way to
> choose which memory accesses do not need to be tracked in the TSX
> read set. Add TSX suspend load tracking CPUID feature flag TSXLDTRK
> for enumeration.
> 
> A processor supports Intel TSX suspend load address tracking if
> CPUID.0x07.0x0:EDX[16] is present. Two instructions XSUSLDTRK, XRESLDTRK
> are available when this feature is present.
> 
> The CPU feature flag is shown as "tsxldtrk" in /proc/cpuinfo.
> 
> Detailed information on the instructions and CPUID feature flag TSXLDTRK
> can be found in the latest Intel Architecture Instruction Set Extensions
> and Future Features Programming Reference and Intel 64 and IA-32
> Architectures Software Developer's Manual.
> 
> Signed-off-by: Kyung Min Park <kyung.min.park@intel.com>
> Signed-off-by: Cathy Zhang <cathy.zhang@intel.com>
> ---
>  arch/x86/include/asm/cpufeatures.h | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
> index adf45cf..34b66d7 100644
> --- a/arch/x86/include/asm/cpufeatures.h
> +++ b/arch/x86/include/asm/cpufeatures.h
> @@ -366,6 +366,7 @@
>  #define X86_FEATURE_MD_CLEAR		(18*32+10) /* VERW clears CPU buffers */
>  #define X86_FEATURE_TSX_FORCE_ABORT	(18*32+13) /* "" TSX_FORCE_ABORT */
>  #define X86_FEATURE_SERIALIZE		(18*32+14) /* SERIALIZE instruction */
> +#define X86_FEATURE_TSX_LDTRK           (18*32+16) /* TSX Suspend Load Address Tracking */

No tabs?

:(
Zhang, Cathy July 8, 2020, 8:33 a.m. UTC | #3 
On 7/7/2020 5:40 PM, Greg KH wrote:
> On Tue, Jul 07, 2020 at 10:16:21AM +0800, Cathy Zhang wrote:
>> Intel TSX suspend load tracking instructions aim to give a way to
>> choose which memory accesses do not need to be tracked in the TSX
>> read set. Add TSX suspend load tracking CPUID feature flag TSXLDTRK
>> for enumeration.
>>
>> A processor supports Intel TSX suspend load address tracking if
>> CPUID.0x07.0x0:EDX[16] is present. Two instructions XSUSLDTRK, XRESLDTRK
>> are available when this feature is present.
>>
>> The CPU feature flag is shown as "tsxldtrk" in /proc/cpuinfo.
>>
>> Detailed information on the instructions and CPUID feature flag TSXLDTRK
>> can be found in the latest Intel Architecture Instruction Set Extensions
>> and Future Features Programming Reference and Intel 64 and IA-32
>> Architectures Software Developer's Manual.
>>
>> Signed-off-by: Kyung Min Park <kyung.min.park@intel.com>
>> Signed-off-by: Cathy Zhang <cathy.zhang@intel.com>
>> ---
>>   arch/x86/include/asm/cpufeatures.h | 1 +
>>   1 file changed, 1 insertion(+)
>>
>> diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
>> index adf45cf..34b66d7 100644
>> --- a/arch/x86/include/asm/cpufeatures.h
>> +++ b/arch/x86/include/asm/cpufeatures.h
>> @@ -366,6 +366,7 @@
>>   #define X86_FEATURE_MD_CLEAR		(18*32+10) /* VERW clears CPU buffers */
>>   #define X86_FEATURE_TSX_FORCE_ABORT	(18*32+13) /* "" TSX_FORCE_ABORT */
>>   #define X86_FEATURE_SERIALIZE		(18*32+14) /* SERIALIZE instruction */
>> +#define X86_FEATURE_TSX_LDTRK           (18*32+16) /* TSX Suspend Load Address Tracking */
> No tabs?
>
> :(
Sorry, it's my fault. I wrongly pick up an older kernel patch version, 
the latest one has no such issue. It will be addressed in next version.
diff mbox series

Patch

diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index adf45cf..34b66d7 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -366,6 +366,7 @@ 
 #define X86_FEATURE_MD_CLEAR		(18*32+10) /* VERW clears CPU buffers */
 #define X86_FEATURE_TSX_FORCE_ABORT	(18*32+13) /* "" TSX_FORCE_ABORT */
 #define X86_FEATURE_SERIALIZE		(18*32+14) /* SERIALIZE instruction */
+#define X86_FEATURE_TSX_LDTRK           (18*32+16) /* TSX Suspend Load Address Tracking */
 #define X86_FEATURE_PCONFIG		(18*32+18) /* Intel PCONFIG */
 #define X86_FEATURE_SPEC_CTRL		(18*32+26) /* "" Speculation Control (IBRS + IBPB) */
 #define X86_FEATURE_INTEL_STIBP		(18*32+27) /* "" Single Thread Indirect Branch Predictors */