Message ID | 1fa32b771828098365162a24654c7bbab805500e.1594230107.git-series.maxime@cerno.tech (mailing list archive) |
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Wed, 8 Jul 2020 13:43:05 -0400 (EDT) From: Maxime Ripard <maxime@cerno.tech> To: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>, Eric Anholt <eric@anholt.net> Subject: [PATCH v4 24/78] drm/vc4: hvs: Make sure our channel is reset Date: Wed, 8 Jul 2020 19:41:32 +0200 Message-Id: <1fa32b771828098365162a24654c7bbab805500e.1594230107.git-series.maxime@cerno.tech> X-Mailer: git-send-email 2.26.2 In-Reply-To: <cover.7a1aa1784976093af26cb31fd283cf5b3ed568bb.1594230107.git-series.maxime@cerno.tech> References: <cover.7a1aa1784976093af26cb31fd283cf5b3ed568bb.1594230107.git-series.maxime@cerno.tech> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200708_134307_977572_50693E4A X-CRM114-Status: UNSURE ( 8.23 ) X-CRM114-Notice: Please train this message. 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Series |
drm/vc4: Support BCM2711 Display Pipeline
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Hi Maxime On Wed, 8 Jul 2020 at 18:43, Maxime Ripard <maxime@cerno.tech> wrote: > > In order to clear our intermediate FIFOs that might end up with a stale > pixel, let's make sure our FIFO channel is reset everytime our channel is > setup. Minor nit pick: s/everytime/every time > Signed-off-by: Maxime Ripard <maxime@cerno.tech> Reviewed-by: Dave Stevenson <dave.stevenson@raspberrypi.com> > --- > drivers/gpu/drm/vc4/vc4_hvs.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/gpu/drm/vc4/vc4_hvs.c b/drivers/gpu/drm/vc4/vc4_hvs.c > index c7de77afbf0a..64b9d72471ef 100644 > --- a/drivers/gpu/drm/vc4/vc4_hvs.c > +++ b/drivers/gpu/drm/vc4/vc4_hvs.c > @@ -205,6 +205,10 @@ static int vc4_hvs_init_channel(struct vc4_dev *vc4, struct drm_crtc *crtc, > u32 dispbkgndx; > u32 dispctrl; > > + HVS_WRITE(SCALER_DISPCTRLX(chan), 0); > + HVS_WRITE(SCALER_DISPCTRLX(chan), SCALER_DISPCTRLX_RESET); > + HVS_WRITE(SCALER_DISPCTRLX(chan), 0); > + > /* Turn on the scaler, which will wait for vstart to start > * compositing. > * When feeding the transposer, we should operate in oneshot > -- > git-series 0.9.1
diff --git a/drivers/gpu/drm/vc4/vc4_hvs.c b/drivers/gpu/drm/vc4/vc4_hvs.c index c7de77afbf0a..64b9d72471ef 100644 --- a/drivers/gpu/drm/vc4/vc4_hvs.c +++ b/drivers/gpu/drm/vc4/vc4_hvs.c @@ -205,6 +205,10 @@ static int vc4_hvs_init_channel(struct vc4_dev *vc4, struct drm_crtc *crtc, u32 dispbkgndx; u32 dispctrl; + HVS_WRITE(SCALER_DISPCTRLX(chan), 0); + HVS_WRITE(SCALER_DISPCTRLX(chan), SCALER_DISPCTRLX_RESET); + HVS_WRITE(SCALER_DISPCTRLX(chan), 0); + /* Turn on the scaler, which will wait for vstart to start * compositing. * When feeding the transposer, we should operate in oneshot
In order to clear our intermediate FIFOs that might end up with a stale pixel, let's make sure our FIFO channel is reset everytime our channel is setup. Signed-off-by: Maxime Ripard <maxime@cerno.tech> --- drivers/gpu/drm/vc4/vc4_hvs.c | 4 ++++ 1 file changed, 4 insertions(+)