| Message ID | 20200708205512.21625-1-jose.souza@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v4,1/5] drm/i915/display: Replace drm_i915_private in voltage swing functions by intel_encoder | expand |
On Wed, Jul 08, 2020 at 01:55:08PM -0700, José Roberto de Souza wrote: > intel_encoder will be needed inside of vswing functions in a future > patch, so here doing this change in all vswing functions since HSW. > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 164 +++++++++++++---------- > 1 file changed, 95 insertions(+), 69 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > index 5773ebefffc7..e80319aa7cf0 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -707,8 +707,10 @@ static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr2[] = > }; > > static const struct ddi_buf_trans * > -bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) > +bdw_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) > { > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > + > if (dev_priv->vbt.edp.low_vswing) { > *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp); > return bdw_ddi_translations_edp; > @@ -719,8 +721,10 @@ bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) > } > > static const struct ddi_buf_trans * > -skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) > +skl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) > { > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > + > if (IS_SKL_ULX(dev_priv)) { > *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp); > return skl_y_ddi_translations_dp; > @@ -734,8 +738,10 @@ skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) > } > > static const struct ddi_buf_trans * > -kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) > +kbl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) > { > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > + > if (IS_KBL_ULX(dev_priv) || > IS_CFL_ULX(dev_priv) || > IS_CML_ULX(dev_priv)) { > @@ -753,8 +759,10 @@ kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) > } > > static const struct ddi_buf_trans * > -skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) > +skl_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) > { > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > + > if (dev_priv->vbt.edp.low_vswing) { > if (IS_SKL_ULX(dev_priv) || > IS_KBL_ULX(dev_priv) || > @@ -777,9 +785,9 @@ skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) > if (IS_KABYLAKE(dev_priv) || > IS_COFFEELAKE(dev_priv) || > IS_COMETLAKE(dev_priv)) > - return kbl_get_buf_trans_dp(dev_priv, n_entries); > + return kbl_get_buf_trans_dp(encoder, n_entries); > else > - return skl_get_buf_trans_dp(dev_priv, n_entries); > + return skl_get_buf_trans_dp(encoder, n_entries); > } > > static const struct ddi_buf_trans * > @@ -807,19 +815,21 @@ static int skl_buf_trans_num_entries(enum port port, int n_entries) > } > > static const struct ddi_buf_trans * > -intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv, > +intel_ddi_get_buf_trans_dp(struct intel_encoder *encoder, > enum port port, int *n_entries) > { > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > + > if (IS_KABYLAKE(dev_priv) || > IS_COFFEELAKE(dev_priv) || > IS_COMETLAKE(dev_priv)) { > const struct ddi_buf_trans *ddi_translations = > - kbl_get_buf_trans_dp(dev_priv, n_entries); > + kbl_get_buf_trans_dp(encoder, n_entries); > *n_entries = skl_buf_trans_num_entries(port, *n_entries); > return ddi_translations; > } else if (IS_SKYLAKE(dev_priv)) { > const struct ddi_buf_trans *ddi_translations = > - skl_get_buf_trans_dp(dev_priv, n_entries); > + skl_get_buf_trans_dp(encoder, n_entries); > *n_entries = skl_buf_trans_num_entries(port, *n_entries); > return ddi_translations; > } else if (IS_BROADWELL(dev_priv)) { > @@ -835,16 +845,18 @@ intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv, > } > > static const struct ddi_buf_trans * > -intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv, > +intel_ddi_get_buf_trans_edp(struct intel_encoder *encoder, > enum port port, int *n_entries) > { > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > + > if (IS_GEN9_BC(dev_priv)) { > const struct ddi_buf_trans *ddi_translations = > - skl_get_buf_trans_edp(dev_priv, n_entries); > + skl_get_buf_trans_edp(encoder, n_entries); > *n_entries = skl_buf_trans_num_entries(port, *n_entries); > return ddi_translations; > } else if (IS_BROADWELL(dev_priv)) { > - return bdw_get_buf_trans_edp(dev_priv, n_entries); > + return bdw_get_buf_trans_edp(encoder, n_entries); > } else if (IS_HASWELL(dev_priv)) { > *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp); > return hsw_ddi_translations_dp; > @@ -871,9 +883,11 @@ intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv, > } > > static const struct ddi_buf_trans * > -intel_ddi_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, > +intel_ddi_get_buf_trans_hdmi(struct intel_encoder *encoder, > int *n_entries) > { > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > + > if (IS_GEN9_BC(dev_priv)) { > return skl_get_buf_trans_hdmi(dev_priv, n_entries); > } else if (IS_BROADWELL(dev_priv)) { > @@ -889,33 +903,36 @@ intel_ddi_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, > } > > static const struct bxt_ddi_buf_trans * > -bxt_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) > +bxt_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) > { > *n_entries = ARRAY_SIZE(bxt_ddi_translations_dp); > return bxt_ddi_translations_dp; > } > > static const struct bxt_ddi_buf_trans * > -bxt_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) > +bxt_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) > { > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > + > if (dev_priv->vbt.edp.low_vswing) { > *n_entries = ARRAY_SIZE(bxt_ddi_translations_edp); > return bxt_ddi_translations_edp; > } > > - return bxt_get_buf_trans_dp(dev_priv, n_entries); > + return bxt_get_buf_trans_dp(encoder, n_entries); > } > > static const struct bxt_ddi_buf_trans * > -bxt_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries) > +bxt_get_buf_trans_hdmi(struct intel_encoder *encoder, int *n_entries) > { > *n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi); > return bxt_ddi_translations_hdmi; > } > > static const struct cnl_ddi_buf_trans * > -cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries) > +cnl_get_buf_trans_hdmi(struct intel_encoder *encoder, int *n_entries) > { > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; > > if (voltage == VOLTAGE_INFO_0_85V) { > @@ -935,8 +952,9 @@ cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries) > } > > static const struct cnl_ddi_buf_trans * > -cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) > +cnl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) > { > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; > > if (voltage == VOLTAGE_INFO_0_85V) { > @@ -956,8 +974,9 @@ cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) > } > > static const struct cnl_ddi_buf_trans * > -cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) > +cnl_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) > { > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; > > if (dev_priv->vbt.edp.low_vswing) { > @@ -976,14 +995,16 @@ cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) > } > return NULL; > } else { > - return cnl_get_buf_trans_dp(dev_priv, n_entries); > + return cnl_get_buf_trans_dp(encoder, n_entries); > } > } > > static const struct cnl_ddi_buf_trans * > -icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate, > +icl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate, > int *n_entries) > { > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > + > if (type == INTEL_OUTPUT_HDMI) { > *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi); > return icl_combo_phy_ddi_translations_hdmi; > @@ -1000,7 +1021,7 @@ icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate, > } > > static const struct icl_mg_phy_ddi_buf_trans * > -icl_get_mg_buf_trans(struct drm_i915_private *dev_priv, int type, int rate, > +icl_get_mg_buf_trans(struct intel_encoder *encoder, int type, int rate, > int *n_entries) > { > if (type == INTEL_OUTPUT_HDMI) { > @@ -1016,7 +1037,7 @@ icl_get_mg_buf_trans(struct drm_i915_private *dev_priv, int type, int rate, > } > > static const struct cnl_ddi_buf_trans * > -ehl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate, > +ehl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate, > int *n_entries) > { > if (type != INTEL_OUTPUT_HDMI && type != INTEL_OUTPUT_EDP) { > @@ -1024,15 +1045,15 @@ ehl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate, > return ehl_combo_phy_ddi_translations_dp; > } > > - return icl_get_combo_buf_trans(dev_priv, type, rate, n_entries); > + return icl_get_combo_buf_trans(encoder, type, rate, n_entries); > } > > static const struct cnl_ddi_buf_trans * > -tgl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate, > +tgl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate, > int *n_entries) > { > if (type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_EDP) { > - return icl_get_combo_buf_trans(dev_priv, type, rate, n_entries); > + return icl_get_combo_buf_trans(encoder, type, rate, n_entries); > } else if (rate > 270000) { > *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr2); > return tgl_combo_phy_ddi_translations_dp_hbr2; > @@ -1043,7 +1064,7 @@ tgl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate, > } > > static const struct tgl_dkl_phy_ddi_buf_trans * > -tgl_get_dkl_buf_trans(struct drm_i915_private *dev_priv, int type, int rate, > +tgl_get_dkl_buf_trans(struct intel_encoder *encoder, int type, int rate, > int *n_entries) > { > if (type == INTEL_OUTPUT_HDMI) { > @@ -1066,34 +1087,34 @@ static int intel_ddi_hdmi_level(struct intel_encoder *encoder) > > if (INTEL_GEN(dev_priv) >= 12) { > if (intel_phy_is_combo(dev_priv, phy)) > - tgl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI, > + tgl_get_combo_buf_trans(encoder, INTEL_OUTPUT_HDMI, > 0, &n_entries); > else > - tgl_get_dkl_buf_trans(dev_priv, INTEL_OUTPUT_HDMI, 0, > + tgl_get_dkl_buf_trans(encoder, INTEL_OUTPUT_HDMI, 0, > &n_entries); > default_entry = n_entries - 1; > } else if (INTEL_GEN(dev_priv) == 11) { > if (intel_phy_is_combo(dev_priv, phy)) > - icl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI, > + icl_get_combo_buf_trans(encoder, INTEL_OUTPUT_HDMI, > 0, &n_entries); > else > - icl_get_mg_buf_trans(dev_priv, INTEL_OUTPUT_HDMI, 0, > + icl_get_mg_buf_trans(encoder, INTEL_OUTPUT_HDMI, 0, > &n_entries); > default_entry = n_entries - 1; > } else if (IS_CANNONLAKE(dev_priv)) { > - cnl_get_buf_trans_hdmi(dev_priv, &n_entries); > + cnl_get_buf_trans_hdmi(encoder, &n_entries); > default_entry = n_entries - 1; > } else if (IS_GEN9_LP(dev_priv)) { > - bxt_get_buf_trans_hdmi(dev_priv, &n_entries); > + bxt_get_buf_trans_hdmi(encoder, &n_entries); > default_entry = n_entries - 1; > } else if (IS_GEN9_BC(dev_priv)) { > - intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries); > + intel_ddi_get_buf_trans_hdmi(encoder, &n_entries); > default_entry = 8; > } else if (IS_BROADWELL(dev_priv)) { > - intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries); > + intel_ddi_get_buf_trans_hdmi(encoder, &n_entries); > default_entry = 7; > } else if (IS_HASWELL(dev_priv)) { > - intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries); > + intel_ddi_get_buf_trans_hdmi(encoder, &n_entries); > default_entry = 6; > } else { > drm_WARN(&dev_priv->drm, 1, "ddi translation table missing\n"); > @@ -1131,10 +1152,10 @@ static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder, > ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv, > &n_entries); > else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) > - ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port, > + ddi_translations = intel_ddi_get_buf_trans_edp(encoder, port, > &n_entries); > else > - ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port, > + ddi_translations = intel_ddi_get_buf_trans_dp(encoder, port, > &n_entries); > > /* If we're boosting the current, set bit 31 of trans1 */ > @@ -1163,7 +1184,7 @@ static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, > enum port port = encoder->port; > const struct ddi_buf_trans *ddi_translations; > > - ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries); > + ddi_translations = intel_ddi_get_buf_trans_hdmi(encoder, &n_entries); > > if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) > return; > @@ -2098,11 +2119,15 @@ static void skl_ddi_set_iboost(struct intel_encoder *encoder, > int n_entries; > > if (type == INTEL_OUTPUT_HDMI) > - ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries); > + ddi_translations = intel_ddi_get_buf_trans_hdmi(encoder, &n_entries); > else if (type == INTEL_OUTPUT_EDP) > - ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries); > + ddi_translations = intel_ddi_get_buf_trans_edp(encoder, > + port, > + &n_entries); > else > - ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries); > + ddi_translations = intel_ddi_get_buf_trans_dp(encoder, > + port, > + &n_entries); > > if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) > return; > @@ -2133,11 +2158,11 @@ static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder, > int n_entries; > > if (type == INTEL_OUTPUT_HDMI) > - ddi_translations = bxt_get_buf_trans_hdmi(dev_priv, &n_entries); > + ddi_translations = bxt_get_buf_trans_hdmi(encoder, &n_entries); > else if (type == INTEL_OUTPUT_EDP) > - ddi_translations = bxt_get_buf_trans_edp(dev_priv, &n_entries); > + ddi_translations = bxt_get_buf_trans_edp(encoder, &n_entries); > else > - ddi_translations = bxt_get_buf_trans_dp(dev_priv, &n_entries); > + ddi_translations = bxt_get_buf_trans_dp(encoder, &n_entries); > > if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) > return; > @@ -2161,36 +2186,36 @@ static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp) > > if (INTEL_GEN(dev_priv) >= 12) { > if (intel_phy_is_combo(dev_priv, phy)) > - tgl_get_combo_buf_trans(dev_priv, encoder->type, > + tgl_get_combo_buf_trans(encoder, encoder->type, > intel_dp->link_rate, &n_entries); > else > - tgl_get_dkl_buf_trans(dev_priv, encoder->type, > + tgl_get_dkl_buf_trans(encoder, encoder->type, > intel_dp->link_rate, &n_entries); > } else if (INTEL_GEN(dev_priv) == 11) { > if (IS_ELKHARTLAKE(dev_priv)) > - ehl_get_combo_buf_trans(dev_priv, encoder->type, > + ehl_get_combo_buf_trans(encoder, encoder->type, > intel_dp->link_rate, &n_entries); > else if (intel_phy_is_combo(dev_priv, phy)) > - icl_get_combo_buf_trans(dev_priv, encoder->type, > + icl_get_combo_buf_trans(encoder, encoder->type, > intel_dp->link_rate, &n_entries); > else > - icl_get_mg_buf_trans(dev_priv, encoder->type, > + icl_get_mg_buf_trans(encoder, encoder->type, > intel_dp->link_rate, &n_entries); > } else if (IS_CANNONLAKE(dev_priv)) { > if (encoder->type == INTEL_OUTPUT_EDP) > - cnl_get_buf_trans_edp(dev_priv, &n_entries); > + cnl_get_buf_trans_edp(encoder, &n_entries); > else > - cnl_get_buf_trans_dp(dev_priv, &n_entries); > + cnl_get_buf_trans_dp(encoder, &n_entries); > } else if (IS_GEN9_LP(dev_priv)) { > if (encoder->type == INTEL_OUTPUT_EDP) > - bxt_get_buf_trans_edp(dev_priv, &n_entries); > + bxt_get_buf_trans_edp(encoder, &n_entries); > else > - bxt_get_buf_trans_dp(dev_priv, &n_entries); > + bxt_get_buf_trans_dp(encoder, &n_entries); > } else { > if (encoder->type == INTEL_OUTPUT_EDP) > - intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries); > + intel_ddi_get_buf_trans_edp(encoder, port, &n_entries); > else > - intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries); > + intel_ddi_get_buf_trans_dp(encoder, port, &n_entries); > } > > if (drm_WARN_ON(&dev_priv->drm, n_entries < 1)) > @@ -2223,11 +2248,11 @@ static void cnl_ddi_vswing_program(struct intel_encoder *encoder, > u32 val; > > if (type == INTEL_OUTPUT_HDMI) > - ddi_translations = cnl_get_buf_trans_hdmi(dev_priv, &n_entries); > + ddi_translations = cnl_get_buf_trans_hdmi(encoder, &n_entries); > else if (type == INTEL_OUTPUT_EDP) > - ddi_translations = cnl_get_buf_trans_edp(dev_priv, &n_entries); > + ddi_translations = cnl_get_buf_trans_edp(encoder, &n_entries); > else > - ddi_translations = cnl_get_buf_trans_dp(dev_priv, &n_entries); > + ddi_translations = cnl_get_buf_trans_dp(encoder, &n_entries); > > if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) > return; > @@ -2344,22 +2369,23 @@ static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder, > intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val); > } > > -static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv, > - u32 level, enum phy phy, int type, > - int rate) > +static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, > + u32 level, enum phy phy, int type, > + int rate) > { > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > const struct cnl_ddi_buf_trans *ddi_translations = NULL; > u32 n_entries, val; > int ln; > > if (INTEL_GEN(dev_priv) >= 12) > - ddi_translations = tgl_get_combo_buf_trans(dev_priv, type, rate, > + ddi_translations = tgl_get_combo_buf_trans(encoder, type, rate, > &n_entries); > else if (IS_ELKHARTLAKE(dev_priv)) > - ddi_translations = ehl_get_combo_buf_trans(dev_priv, type, rate, > + ddi_translations = ehl_get_combo_buf_trans(encoder, type, rate, > &n_entries); > else > - ddi_translations = icl_get_combo_buf_trans(dev_priv, type, rate, > + ddi_translations = icl_get_combo_buf_trans(encoder, type, rate, > &n_entries); > if (!ddi_translations) > return; > @@ -2471,7 +2497,7 @@ static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder, > intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); > > /* 5. Program swing and de-emphasis */ > - icl_ddi_combo_vswing_program(dev_priv, level, phy, type, rate); > + icl_ddi_combo_vswing_program(encoder, level, phy, type, rate); > > /* 6. Set training enable to trigger update */ > val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy)); > @@ -2495,7 +2521,7 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, > rate = intel_dp->link_rate; > } > > - ddi_translations = icl_get_mg_buf_trans(dev_priv, type, rate, > + ddi_translations = icl_get_mg_buf_trans(encoder, type, rate, > &n_entries); > /* The table does not have values for level 3 and level 9. */ > if (level >= n_entries || level == 3 || level == 9) { > @@ -2640,7 +2666,7 @@ tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, int link_clock, > rate = intel_dp->link_rate; > } > > - ddi_translations = tgl_get_dkl_buf_trans(dev_priv, encoder->type, rate, > + ddi_translations = tgl_get_dkl_buf_trans(encoder, encoder->type, rate, > &n_entries); > > if (level >= n_entries) > -- > 2.27.0 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Thu, 2020-07-09 at 18:59 +0000, Patchwork wrote: > == Series Details == > > Series: series starting with [v4,1/5] drm/i915/display: Replace drm_i915_private in voltage swing functions by intel_encoder (rev2) > URL : https://patchwork.freedesktop.org/series/79265/ > State : success > > == Summary == > > CI Bug Log - changes from CI_DRM_8719_full -> Patchwork_18124_full > ==================================================== > > Summary > ------- > > **SUCCESS** > > No regressions found. Pushed the 3 first patches to dinq, thanks for the reviews. > > > > Known issues > ------------ > > Here are the changes found in Patchwork_18124_full that come from known issues: > > ### IGT changes ### > > #### Issues hit #### > > * igt@gem_ctx_persistence@engines-mixed-process@vecs0: > - shard-skl: [PASS][1] -> [FAIL][2] ([i915#1528]) > [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-skl6/igt@gem_ctx_persistence@engines-mixed-process@vecs0.html > [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-skl8/igt@gem_ctx_persistence@engines-mixed-process@vecs0.html > > * igt@gem_eio@kms: > - shard-snb: [PASS][3] -> [DMESG-WARN][4] ([i915#1982]) > [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-snb1/igt@gem_eio@kms.html > [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-snb6/igt@gem_eio@kms.html > > * igt@gem_exec_balancer@bonded-early: > - shard-kbl: [PASS][5] -> [FAIL][6] ([i915#2079]) > [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-kbl4/igt@gem_exec_balancer@bonded-early.html > [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-kbl6/igt@gem_exec_balancer@bonded-early.html > > * igt@gem_exec_params@invalid-fence-in: > - shard-kbl: [PASS][7] -> [DMESG-WARN][8] ([i915#93] / [i915#95]) +4 similar issues > [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-kbl7/igt@gem_exec_params@invalid-fence-in.html > [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-kbl2/igt@gem_exec_params@invalid-fence-in.html > > * igt@gem_exec_reloc@basic-concurrent0: > - shard-glk: [PASS][9] -> [FAIL][10] ([i915#1930]) > [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-glk3/igt@gem_exec_reloc@basic-concurrent0.html > [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-glk5/igt@gem_exec_reloc@basic-concurrent0.html > > * igt@i915_pm_backlight@fade_with_suspend: > - shard-skl: [PASS][11] -> [INCOMPLETE][12] ([i915#69]) > [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-skl5/igt@i915_pm_backlight@fade_with_suspend.html > [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-skl1/igt@i915_pm_backlight@fade_with_suspend.html > > * igt@i915_selftest@mock@requests: > - shard-apl: [PASS][13] -> [INCOMPLETE][14] ([i915#1635] / [i915#2110]) > [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-apl3/igt@i915_selftest@mock@requests.html > [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-apl2/igt@i915_selftest@mock@requests.html > > * igt@kms_big_fb@x-tiled-64bpp-rotate-0: > - shard-apl: [PASS][15] -> [DMESG-WARN][16] ([i915#1982]) > [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-apl3/igt@kms_big_fb@x-tiled-64bpp-rotate-0.html > [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-apl2/igt@kms_big_fb@x-tiled-64bpp-rotate-0.html > > * igt@kms_big_fb@y-tiled-16bpp-rotate-0: > - shard-skl: [PASS][17] -> [DMESG-WARN][18] ([i915#1982]) +8 similar issues > [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-skl1/igt@kms_big_fb@y-tiled-16bpp-rotate-0.html > [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-skl2/igt@kms_big_fb@y-tiled-16bpp-rotate-0.html > > * igt@kms_big_fb@y-tiled-64bpp-rotate-0: > - shard-glk: [PASS][19] -> [DMESG-FAIL][20] ([i915#118] / [i915#95]) > [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-glk6/igt@kms_big_fb@y-tiled-64bpp-rotate-0.html > [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-glk8/igt@kms_big_fb@y-tiled-64bpp-rotate-0.html > > * igt@kms_cursor_crc@pipe-a-cursor-128x42-sliding: > - shard-apl: [PASS][21] -> [DMESG-WARN][22] ([i915#1635] / [i915#95]) +15 similar issues > [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-apl7/igt@kms_cursor_crc@pipe-a-cursor-128x42-sliding.html > [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-apl4/igt@kms_cursor_crc@pipe-a-cursor-128x42-sliding.html > > * igt@kms_cursor_crc@pipe-a-cursor-suspend: > - shard-kbl: [PASS][23] -> [DMESG-WARN][24] ([i915#180]) +4 similar issues > [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-kbl1/igt@kms_cursor_crc@pipe-a-cursor-suspend.html > [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-kbl1/igt@kms_cursor_crc@pipe-a-cursor-suspend.html > - shard-glk: [PASS][25] -> [FAIL][26] ([i915#54]) > [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-glk3/igt@kms_cursor_crc@pipe-a-cursor-suspend.html > [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-glk8/igt@kms_cursor_crc@pipe-a-cursor-suspend.html > > * igt@kms_cursor_legacy@cursora-vs-flipa-toggle: > - shard-tglb: [PASS][27] -> [DMESG-WARN][28] ([i915#402]) > [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-tglb5/igt@kms_cursor_legacy@cursora-vs-flipa-toggle.html > [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-tglb2/igt@kms_cursor_legacy@cursora-vs-flipa-toggle.html > > * igt@kms_flip@flip-vs-blocking-wf-vblank@a-edp1: > - shard-tglb: [PASS][29] -> [FAIL][30] ([i915#2122]) > [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-tglb2/igt@kms_flip@flip-vs-blocking-wf-vblank@a-edp1.html > [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-tglb3/igt@kms_flip@flip-vs-blocking-wf-vblank@a-edp1.html > > * igt@kms_flip@plain-flip-fb-recreate@b-edp1: > - shard-skl: [PASS][31] -> [FAIL][32] ([i915#2122]) > [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-skl4/igt@kms_flip@plain-flip-fb-recreate@b-edp1.html > [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-skl10/igt@kms_flip@plain-flip-fb-recreate@b-edp1.html > > * igt@kms_frontbuffer_tracking@basic: > - shard-glk: [PASS][33] -> [DMESG-WARN][34] ([i915#1982]) > [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-glk8/igt@kms_frontbuffer_tracking@basic.html > [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-glk4/igt@kms_frontbuffer_tracking@basic.html > > * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-blt: > - shard-tglb: [PASS][35] -> [DMESG-WARN][36] ([i915#1982]) > [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-tglb8/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-blt.html > [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-tglb5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-blt.html > > * igt@kms_psr@no_drrs: > - shard-iclb: [PASS][37] -> [FAIL][38] ([i915#173]) > [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-iclb2/igt@kms_psr@no_drrs.html > [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-iclb1/igt@kms_psr@no_drrs.html > > * igt@kms_psr@psr2_cursor_mmap_cpu: > - shard-iclb: [PASS][39] -> [SKIP][40] ([fdo#109441]) +3 similar issues > [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html > [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-iclb1/igt@kms_psr@psr2_cursor_mmap_cpu.html > > * igt@perf_pmu@semaphore-busy@rcs0: > - shard-kbl: [PASS][41] -> [FAIL][42] ([i915#1820]) > [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-kbl7/igt@perf_pmu@semaphore-busy@rcs0.html > [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-kbl2/igt@perf_pmu@semaphore-busy@rcs0.html > > > #### Possible fixes #### > > * igt@gem_ctx_isolation@preservation-s3@bcs0: > - shard-kbl: [DMESG-WARN][43] ([i915#180]) -> [PASS][44] +4 similar issues > [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-kbl4/igt@gem_ctx_isolation@preservation-s3@bcs0.html > [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-kbl3/igt@gem_ctx_isolation@preservation-s3@bcs0.html > > * igt@gem_eio@in-flight-contexts-10ms: > - shard-hsw: [TIMEOUT][45] ([i915#1958] / [i915#1976] / [i915#2119]) -> [PASS][46] > [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-hsw2/igt@gem_eio@in-flight-contexts-10ms.html > [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-hsw7/igt@gem_eio@in-flight-contexts-10ms.html > > * igt@gem_eio@reset-stress: > - shard-hsw: [INCOMPLETE][47] ([CI#80]) -> [PASS][48] > [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-hsw2/igt@gem_eio@reset-stress.html > [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-hsw7/igt@gem_eio@reset-stress.html > > * igt@gem_exec_whisper@basic-normal: > - shard-glk: [DMESG-WARN][49] ([i915#118] / [i915#95]) -> [PASS][50] > [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-glk9/igt@gem_exec_whisper@basic-normal.html > [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-glk7/igt@gem_exec_whisper@basic-normal.html > > * igt@i915_module_load@reload: > - shard-tglb: [DMESG-WARN][51] ([i915#402]) -> [PASS][52] > [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-tglb2/igt@i915_module_load@reload.html > [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-tglb3/igt@i915_module_load@reload.html > > * igt@i915_selftest@mock@requests: > - shard-skl: [INCOMPLETE][53] ([i915#198] / [i915#2110]) -> [PASS][54] > [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-skl8/igt@i915_selftest@mock@requests.html > [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-skl1/igt@i915_selftest@mock@requests.html > > * igt@kms_big_fb@x-tiled-64bpp-rotate-0: > - shard-glk: [DMESG-FAIL][55] ([i915#118] / [i915#95]) -> [PASS][56] +1 similar issue > [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-glk8/igt@kms_big_fb@x-tiled-64bpp-rotate-0.html > [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-glk4/igt@kms_big_fb@x-tiled-64bpp-rotate-0.html > > * igt@kms_color@pipe-b-ctm-negative: > - shard-skl: [DMESG-WARN][57] ([i915#1982]) -> [PASS][58] +6 similar issues > [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-skl2/igt@kms_color@pipe-b-ctm-negative.html > [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-skl6/igt@kms_color@pipe-b-ctm-negative.html > > * igt@kms_cursor_edge_walk@pipe-b-128x128-left-edge: > - shard-glk: [DMESG-WARN][59] ([i915#1982]) -> [PASS][60] +1 similar issue > [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-glk7/igt@kms_cursor_edge_walk@pipe-b-128x128-left-edge.html > [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-glk9/igt@kms_cursor_edge_walk@pipe-b-128x128-left-edge.html > > * igt@kms_cursor_legacy@flip-vs-cursor-crc-atomic: > - shard-tglb: [DMESG-WARN][61] ([i915#1982]) -> [PASS][62] +1 similar issue > [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-tglb2/igt@kms_cursor_legacy@flip-vs-cursor-crc-atomic.html > [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-tglb3/igt@kms_cursor_legacy@flip-vs-cursor-crc-atomic.html > > * igt@kms_draw_crc@draw-method-rgb565-pwrite-untiled: > - shard-apl: [DMESG-WARN][63] ([i915#1982]) -> [PASS][64] > [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-apl1/igt@kms_draw_crc@draw-method-rgb565-pwrite-untiled.html > [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-apl6/igt@kms_draw_crc@draw-method-rgb565-pwrite-untiled.html > > * igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible@ab-vga1-hdmi-a1: > - shard-hsw: [DMESG-WARN][65] ([i915#1982]) -> [PASS][66] > [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-hsw6/igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible@ab-vga1-hdmi-a1.html > [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-hsw6/igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible@ab-vga1-hdmi-a1.html > > * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt: > - shard-apl: [DMESG-WARN][67] ([i915#1635] / [i915#95]) -> [PASS][68] +13 similar issues > [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-apl2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt.html > [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-apl3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt.html > > * igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-msflip-blt: > - shard-tglb: [SKIP][69] ([i915#668]) -> [PASS][70] +2 similar issues > [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-tglb2/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-msflip-blt.html > [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-tglb3/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-msflip-blt.html > > * igt@kms_hdr@bpc-switch: > - shard-skl: [FAIL][71] ([i915#1188]) -> [PASS][72] > [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-skl10/igt@kms_hdr@bpc-switch.html > [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-skl5/igt@kms_hdr@bpc-switch.html > > * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: > - shard-skl: [FAIL][73] ([fdo#108145] / [i915#265]) -> [PASS][74] > [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-skl4/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html > [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-skl8/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html > > * igt@kms_psr@psr2_cursor_render: > - shard-iclb: [SKIP][75] ([fdo#109441]) -> [PASS][76] +2 similar issues > [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-iclb5/igt@kms_psr@psr2_cursor_render.html > [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-iclb2/igt@kms_psr@psr2_cursor_render.html > > > #### Warnings #### > > * igt@i915_pm_dc@dc3co-vpb-simulation: > - shard-iclb: [SKIP][77] ([i915#658]) -> [SKIP][78] ([i915#588]) > [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-iclb1/igt@i915_pm_dc@dc3co-vpb-simulation.html > [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html > > * igt@kms_color_chamelium@pipe-b-ctm-0-5: > - shard-apl: [SKIP][79] ([fdo#109271] / [fdo#111827] / [i915#1635]) -> [SKIP][80] ([fdo#109271] / [fdo#111827]) > [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-apl7/igt@kms_color_chamelium@pipe-b-ctm-0-5.html > [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-apl2/igt@kms_color_chamelium@pipe-b-ctm-0-5.html > > * igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible: > - shard-apl: [SKIP][81] ([fdo#109271] / [i915#1635]) -> [SKIP][82] ([fdo#109271]) +3 similar issues > [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-apl7/igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible.html > [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-apl8/igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible.html > > * igt@kms_flip@flip-vs-suspend@a-edp1: > - shard-tglb: [DMESG-WARN][83] ([i915#1602] / [i915#1887]) -> [INCOMPLETE][84] ([i915#1602] / [i915#1887] / [i915#456]) > [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-tglb8/igt@kms_flip@flip-vs-suspend@a-edp1.html > [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-tglb5/igt@kms_flip@flip-vs-suspend@a-edp1.html > > * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-pwrite: > - shard-apl: [SKIP][85] ([fdo#109271]) -> [SKIP][86] ([fdo#109271] / [i915#1635]) > [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-apl3/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-pwrite.html > [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-apl1/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-pwrite.html > > * igt@kms_plane_alpha_blend@pipe-a-alpha-basic: > - shard-apl: [DMESG-FAIL][87] ([fdo#108145] / [i915#1982]) -> [FAIL][88] ([fdo#108145] / [i915#265]) > [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-apl4/igt@kms_plane_alpha_blend@pipe-a-alpha-basic.html > [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-apl1/igt@kms_plane_alpha_blend@pipe-a-alpha-basic.html > > * igt@runner@aborted: > - shard-apl: ([FAIL][89], [FAIL][90]) ([i915#1610] / [i915#1635] / [i915#2110]) -> [FAIL][91] ([i915#1635] / [i915#2110]) > [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-apl2/igt@runner@aborted.html > [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-apl4/igt@runner@aborted.html > [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-apl2/igt@runner@aborted.html > - shard-tglb: ([FAIL][92], [FAIL][93]) ([i915#2110] / [i915#2150]) -> ([FAIL][94], [FAIL][95]) ([i915#1764] / [i915#2110] / [i915#2150]) > [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-tglb8/igt@runner@aborted.html > [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8719/shard-tglb2/igt@runner@aborted.html > [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-tglb5/igt@runner@aborted.html > [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/shard-tglb3/igt@runner@aborted.html > > > [CI#80]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/80 > [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 > [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 > [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 > [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 > [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118 > [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 > [i915#1528]: https://gitlab.freedesktop.org/drm/intel/issues/1528 > [i915#1602]: https://gitlab.freedesktop.org/drm/intel/issues/1602 > [i915#1610]: https://gitlab.freedesktop.org/drm/intel/issues/1610 > [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635 > [i915#173]: https://gitlab.freedesktop.org/drm/intel/issues/173 > [i915#1764]: https://gitlab.freedesktop.org/drm/intel/issues/1764 > [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 > [i915#1820]: https://gitlab.freedesktop.org/drm/intel/issues/1820 > [i915#1887]: https://gitlab.freedesktop.org/drm/intel/issues/1887 > [i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930 > [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958 > [i915#1976]: https://gitlab.freedesktop.org/drm/intel/issues/1976 > [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198 > [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 > [i915#2079]: https://gitlab.freedesktop.org/drm/intel/issues/2079 > [i915#2110]: https://gitlab.freedesktop.org/drm/intel/issues/2110 > [i915#2119]: https://gitlab.freedesktop.org/drm/intel/issues/2119 > [i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122 > [i915#2150]: https://gitlab.freedesktop.org/drm/intel/issues/2150 > [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 > [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 > [i915#456]: https://gitlab.freedesktop.org/drm/intel/issues/456 > [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 > [i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588 > [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 > [i915#668]: https://gitlab.freedesktop.org/drm/intel/issues/668 > [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 > [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93 > [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 > > > Participating hosts (10 -> 10) > ------------------------------ > > No changes in participating hosts > > > Build changes > ------------- > > * Linux: CI_DRM_8719 -> Patchwork_18124 > > CI-20190529: 20190529 > CI_DRM_8719: 6ca80d83ae657da395ab20034f0f66209b456127 @ git://anongit.freedesktop.org/gfx-ci/linux > IGT_5729: a048d54f58dd70b07dbeb4541b273ec230ddb586 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools > Patchwork_18124: fc1806ac58ba125b3ae1694ecf14b24a6dc5ffa0 @ git://anongit.freedesktop.org/gfx-ci/linux > piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit > > == Logs == > > For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18124/index.html
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 5773ebefffc7..e80319aa7cf0 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -707,8 +707,10 @@ static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr2[] = }; static const struct ddi_buf_trans * -bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) +bdw_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) { + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + if (dev_priv->vbt.edp.low_vswing) { *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp); return bdw_ddi_translations_edp; @@ -719,8 +721,10 @@ bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) } static const struct ddi_buf_trans * -skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) +skl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) { + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + if (IS_SKL_ULX(dev_priv)) { *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp); return skl_y_ddi_translations_dp; @@ -734,8 +738,10 @@ skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) } static const struct ddi_buf_trans * -kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) +kbl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) { + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + if (IS_KBL_ULX(dev_priv) || IS_CFL_ULX(dev_priv) || IS_CML_ULX(dev_priv)) { @@ -753,8 +759,10 @@ kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) } static const struct ddi_buf_trans * -skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) +skl_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) { + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + if (dev_priv->vbt.edp.low_vswing) { if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv) || @@ -777,9 +785,9 @@ skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv)) - return kbl_get_buf_trans_dp(dev_priv, n_entries); + return kbl_get_buf_trans_dp(encoder, n_entries); else - return skl_get_buf_trans_dp(dev_priv, n_entries); + return skl_get_buf_trans_dp(encoder, n_entries); } static const struct ddi_buf_trans * @@ -807,19 +815,21 @@ static int skl_buf_trans_num_entries(enum port port, int n_entries) } static const struct ddi_buf_trans * -intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv, +intel_ddi_get_buf_trans_dp(struct intel_encoder *encoder, enum port port, int *n_entries) { + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv)) { const struct ddi_buf_trans *ddi_translations = - kbl_get_buf_trans_dp(dev_priv, n_entries); + kbl_get_buf_trans_dp(encoder, n_entries); *n_entries = skl_buf_trans_num_entries(port, *n_entries); return ddi_translations; } else if (IS_SKYLAKE(dev_priv)) { const struct ddi_buf_trans *ddi_translations = - skl_get_buf_trans_dp(dev_priv, n_entries); + skl_get_buf_trans_dp(encoder, n_entries); *n_entries = skl_buf_trans_num_entries(port, *n_entries); return ddi_translations; } else if (IS_BROADWELL(dev_priv)) { @@ -835,16 +845,18 @@ intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv, } static const struct ddi_buf_trans * -intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv, +intel_ddi_get_buf_trans_edp(struct intel_encoder *encoder, enum port port, int *n_entries) { + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + if (IS_GEN9_BC(dev_priv)) { const struct ddi_buf_trans *ddi_translations = - skl_get_buf_trans_edp(dev_priv, n_entries); + skl_get_buf_trans_edp(encoder, n_entries); *n_entries = skl_buf_trans_num_entries(port, *n_entries); return ddi_translations; } else if (IS_BROADWELL(dev_priv)) { - return bdw_get_buf_trans_edp(dev_priv, n_entries); + return bdw_get_buf_trans_edp(encoder, n_entries); } else if (IS_HASWELL(dev_priv)) { *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp); return hsw_ddi_translations_dp; @@ -871,9 +883,11 @@ intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv, } static const struct ddi_buf_trans * -intel_ddi_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, +intel_ddi_get_buf_trans_hdmi(struct intel_encoder *encoder, int *n_entries) { + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + if (IS_GEN9_BC(dev_priv)) { return skl_get_buf_trans_hdmi(dev_priv, n_entries); } else if (IS_BROADWELL(dev_priv)) { @@ -889,33 +903,36 @@ intel_ddi_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, } static const struct bxt_ddi_buf_trans * -bxt_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) +bxt_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) { *n_entries = ARRAY_SIZE(bxt_ddi_translations_dp); return bxt_ddi_translations_dp; } static const struct bxt_ddi_buf_trans * -bxt_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) +bxt_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) { + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + if (dev_priv->vbt.edp.low_vswing) { *n_entries = ARRAY_SIZE(bxt_ddi_translations_edp); return bxt_ddi_translations_edp; } - return bxt_get_buf_trans_dp(dev_priv, n_entries); + return bxt_get_buf_trans_dp(encoder, n_entries); } static const struct bxt_ddi_buf_trans * -bxt_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries) +bxt_get_buf_trans_hdmi(struct intel_encoder *encoder, int *n_entries) { *n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi); return bxt_ddi_translations_hdmi; } static const struct cnl_ddi_buf_trans * -cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries) +cnl_get_buf_trans_hdmi(struct intel_encoder *encoder, int *n_entries) { + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; if (voltage == VOLTAGE_INFO_0_85V) { @@ -935,8 +952,9 @@ cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries) } static const struct cnl_ddi_buf_trans * -cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) +cnl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries) { + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; if (voltage == VOLTAGE_INFO_0_85V) { @@ -956,8 +974,9 @@ cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) } static const struct cnl_ddi_buf_trans * -cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) +cnl_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries) { + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; if (dev_priv->vbt.edp.low_vswing) { @@ -976,14 +995,16 @@ cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) } return NULL; } else { - return cnl_get_buf_trans_dp(dev_priv, n_entries); + return cnl_get_buf_trans_dp(encoder, n_entries); } } static const struct cnl_ddi_buf_trans * -icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate, +icl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate, int *n_entries) { + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + if (type == INTEL_OUTPUT_HDMI) { *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi); return icl_combo_phy_ddi_translations_hdmi; @@ -1000,7 +1021,7 @@ icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate, } static const struct icl_mg_phy_ddi_buf_trans * -icl_get_mg_buf_trans(struct drm_i915_private *dev_priv, int type, int rate, +icl_get_mg_buf_trans(struct intel_encoder *encoder, int type, int rate, int *n_entries) { if (type == INTEL_OUTPUT_HDMI) { @@ -1016,7 +1037,7 @@ icl_get_mg_buf_trans(struct drm_i915_private *dev_priv, int type, int rate, } static const struct cnl_ddi_buf_trans * -ehl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate, +ehl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate, int *n_entries) { if (type != INTEL_OUTPUT_HDMI && type != INTEL_OUTPUT_EDP) { @@ -1024,15 +1045,15 @@ ehl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate, return ehl_combo_phy_ddi_translations_dp; } - return icl_get_combo_buf_trans(dev_priv, type, rate, n_entries); + return icl_get_combo_buf_trans(encoder, type, rate, n_entries); } static const struct cnl_ddi_buf_trans * -tgl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate, +tgl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate, int *n_entries) { if (type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_EDP) { - return icl_get_combo_buf_trans(dev_priv, type, rate, n_entries); + return icl_get_combo_buf_trans(encoder, type, rate, n_entries); } else if (rate > 270000) { *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr2); return tgl_combo_phy_ddi_translations_dp_hbr2; @@ -1043,7 +1064,7 @@ tgl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate, } static const struct tgl_dkl_phy_ddi_buf_trans * -tgl_get_dkl_buf_trans(struct drm_i915_private *dev_priv, int type, int rate, +tgl_get_dkl_buf_trans(struct intel_encoder *encoder, int type, int rate, int *n_entries) { if (type == INTEL_OUTPUT_HDMI) { @@ -1066,34 +1087,34 @@ static int intel_ddi_hdmi_level(struct intel_encoder *encoder) if (INTEL_GEN(dev_priv) >= 12) { if (intel_phy_is_combo(dev_priv, phy)) - tgl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI, + tgl_get_combo_buf_trans(encoder, INTEL_OUTPUT_HDMI, 0, &n_entries); else - tgl_get_dkl_buf_trans(dev_priv, INTEL_OUTPUT_HDMI, 0, + tgl_get_dkl_buf_trans(encoder, INTEL_OUTPUT_HDMI, 0, &n_entries); default_entry = n_entries - 1; } else if (INTEL_GEN(dev_priv) == 11) { if (intel_phy_is_combo(dev_priv, phy)) - icl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI, + icl_get_combo_buf_trans(encoder, INTEL_OUTPUT_HDMI, 0, &n_entries); else - icl_get_mg_buf_trans(dev_priv, INTEL_OUTPUT_HDMI, 0, + icl_get_mg_buf_trans(encoder, INTEL_OUTPUT_HDMI, 0, &n_entries); default_entry = n_entries - 1; } else if (IS_CANNONLAKE(dev_priv)) { - cnl_get_buf_trans_hdmi(dev_priv, &n_entries); + cnl_get_buf_trans_hdmi(encoder, &n_entries); default_entry = n_entries - 1; } else if (IS_GEN9_LP(dev_priv)) { - bxt_get_buf_trans_hdmi(dev_priv, &n_entries); + bxt_get_buf_trans_hdmi(encoder, &n_entries); default_entry = n_entries - 1; } else if (IS_GEN9_BC(dev_priv)) { - intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries); + intel_ddi_get_buf_trans_hdmi(encoder, &n_entries); default_entry = 8; } else if (IS_BROADWELL(dev_priv)) { - intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries); + intel_ddi_get_buf_trans_hdmi(encoder, &n_entries); default_entry = 7; } else if (IS_HASWELL(dev_priv)) { - intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries); + intel_ddi_get_buf_trans_hdmi(encoder, &n_entries); default_entry = 6; } else { drm_WARN(&dev_priv->drm, 1, "ddi translation table missing\n"); @@ -1131,10 +1152,10 @@ static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder, ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv, &n_entries); else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) - ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port, + ddi_translations = intel_ddi_get_buf_trans_edp(encoder, port, &n_entries); else - ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port, + ddi_translations = intel_ddi_get_buf_trans_dp(encoder, port, &n_entries); /* If we're boosting the current, set bit 31 of trans1 */ @@ -1163,7 +1184,7 @@ static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, enum port port = encoder->port; const struct ddi_buf_trans *ddi_translations; - ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries); + ddi_translations = intel_ddi_get_buf_trans_hdmi(encoder, &n_entries); if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) return; @@ -2098,11 +2119,15 @@ static void skl_ddi_set_iboost(struct intel_encoder *encoder, int n_entries; if (type == INTEL_OUTPUT_HDMI) - ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries); + ddi_translations = intel_ddi_get_buf_trans_hdmi(encoder, &n_entries); else if (type == INTEL_OUTPUT_EDP) - ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries); + ddi_translations = intel_ddi_get_buf_trans_edp(encoder, + port, + &n_entries); else - ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries); + ddi_translations = intel_ddi_get_buf_trans_dp(encoder, + port, + &n_entries); if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) return; @@ -2133,11 +2158,11 @@ static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder, int n_entries; if (type == INTEL_OUTPUT_HDMI) - ddi_translations = bxt_get_buf_trans_hdmi(dev_priv, &n_entries); + ddi_translations = bxt_get_buf_trans_hdmi(encoder, &n_entries); else if (type == INTEL_OUTPUT_EDP) - ddi_translations = bxt_get_buf_trans_edp(dev_priv, &n_entries); + ddi_translations = bxt_get_buf_trans_edp(encoder, &n_entries); else - ddi_translations = bxt_get_buf_trans_dp(dev_priv, &n_entries); + ddi_translations = bxt_get_buf_trans_dp(encoder, &n_entries); if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) return; @@ -2161,36 +2186,36 @@ static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp) if (INTEL_GEN(dev_priv) >= 12) { if (intel_phy_is_combo(dev_priv, phy)) - tgl_get_combo_buf_trans(dev_priv, encoder->type, + tgl_get_combo_buf_trans(encoder, encoder->type, intel_dp->link_rate, &n_entries); else - tgl_get_dkl_buf_trans(dev_priv, encoder->type, + tgl_get_dkl_buf_trans(encoder, encoder->type, intel_dp->link_rate, &n_entries); } else if (INTEL_GEN(dev_priv) == 11) { if (IS_ELKHARTLAKE(dev_priv)) - ehl_get_combo_buf_trans(dev_priv, encoder->type, + ehl_get_combo_buf_trans(encoder, encoder->type, intel_dp->link_rate, &n_entries); else if (intel_phy_is_combo(dev_priv, phy)) - icl_get_combo_buf_trans(dev_priv, encoder->type, + icl_get_combo_buf_trans(encoder, encoder->type, intel_dp->link_rate, &n_entries); else - icl_get_mg_buf_trans(dev_priv, encoder->type, + icl_get_mg_buf_trans(encoder, encoder->type, intel_dp->link_rate, &n_entries); } else if (IS_CANNONLAKE(dev_priv)) { if (encoder->type == INTEL_OUTPUT_EDP) - cnl_get_buf_trans_edp(dev_priv, &n_entries); + cnl_get_buf_trans_edp(encoder, &n_entries); else - cnl_get_buf_trans_dp(dev_priv, &n_entries); + cnl_get_buf_trans_dp(encoder, &n_entries); } else if (IS_GEN9_LP(dev_priv)) { if (encoder->type == INTEL_OUTPUT_EDP) - bxt_get_buf_trans_edp(dev_priv, &n_entries); + bxt_get_buf_trans_edp(encoder, &n_entries); else - bxt_get_buf_trans_dp(dev_priv, &n_entries); + bxt_get_buf_trans_dp(encoder, &n_entries); } else { if (encoder->type == INTEL_OUTPUT_EDP) - intel_ddi_get_buf_trans_edp(dev_priv, port, &n_entries); + intel_ddi_get_buf_trans_edp(encoder, port, &n_entries); else - intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries); + intel_ddi_get_buf_trans_dp(encoder, port, &n_entries); } if (drm_WARN_ON(&dev_priv->drm, n_entries < 1)) @@ -2223,11 +2248,11 @@ static void cnl_ddi_vswing_program(struct intel_encoder *encoder, u32 val; if (type == INTEL_OUTPUT_HDMI) - ddi_translations = cnl_get_buf_trans_hdmi(dev_priv, &n_entries); + ddi_translations = cnl_get_buf_trans_hdmi(encoder, &n_entries); else if (type == INTEL_OUTPUT_EDP) - ddi_translations = cnl_get_buf_trans_edp(dev_priv, &n_entries); + ddi_translations = cnl_get_buf_trans_edp(encoder, &n_entries); else - ddi_translations = cnl_get_buf_trans_dp(dev_priv, &n_entries); + ddi_translations = cnl_get_buf_trans_dp(encoder, &n_entries); if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) return; @@ -2344,22 +2369,23 @@ static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder, intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val); } -static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv, - u32 level, enum phy phy, int type, - int rate) +static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, + u32 level, enum phy phy, int type, + int rate) { + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); const struct cnl_ddi_buf_trans *ddi_translations = NULL; u32 n_entries, val; int ln; if (INTEL_GEN(dev_priv) >= 12) - ddi_translations = tgl_get_combo_buf_trans(dev_priv, type, rate, + ddi_translations = tgl_get_combo_buf_trans(encoder, type, rate, &n_entries); else if (IS_ELKHARTLAKE(dev_priv)) - ddi_translations = ehl_get_combo_buf_trans(dev_priv, type, rate, + ddi_translations = ehl_get_combo_buf_trans(encoder, type, rate, &n_entries); else - ddi_translations = icl_get_combo_buf_trans(dev_priv, type, rate, + ddi_translations = icl_get_combo_buf_trans(encoder, type, rate, &n_entries); if (!ddi_translations) return; @@ -2471,7 +2497,7 @@ static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder, intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); /* 5. Program swing and de-emphasis */ - icl_ddi_combo_vswing_program(dev_priv, level, phy, type, rate); + icl_ddi_combo_vswing_program(encoder, level, phy, type, rate); /* 6. Set training enable to trigger update */ val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy)); @@ -2495,7 +2521,7 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, rate = intel_dp->link_rate; } - ddi_translations = icl_get_mg_buf_trans(dev_priv, type, rate, + ddi_translations = icl_get_mg_buf_trans(encoder, type, rate, &n_entries); /* The table does not have values for level 3 and level 9. */ if (level >= n_entries || level == 3 || level == 9) { @@ -2640,7 +2666,7 @@ tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, int link_clock, rate = intel_dp->link_rate; } - ddi_translations = tgl_get_dkl_buf_trans(dev_priv, encoder->type, rate, + ddi_translations = tgl_get_dkl_buf_trans(encoder, encoder->type, rate, &n_entries); if (level >= n_entries)
intel_encoder will be needed inside of vswing functions in a future patch, so here doing this change in all vswing functions since HSW. Signed-off-by: José Roberto de Souza <jose.souza@intel.com> --- drivers/gpu/drm/i915/display/intel_ddi.c | 164 +++++++++++++---------- 1 file changed, 95 insertions(+), 69 deletions(-)