| Message ID | 20200708141856.15776-9-eric.auger@redhat.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | SMMUv3.2 Range-based TLB Invalidation Support | expand |
On Wed, 8 Jul 2020 at 15:20, Eric Auger <eric.auger@redhat.com> wrote: > > The SMMU IIDR register is at 0x018 offset. > > Signed-off-by: Eric Auger <eric.auger@redhat.com> > Fixes: 10a83cb9887 ("hw/arm/smmuv3: Skeleton") > --- > hw/arm/smmuv3-internal.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h > index 5babf72f7d..ef093eaff5 100644 > --- a/hw/arm/smmuv3-internal.h > +++ b/hw/arm/smmuv3-internal.h > @@ -63,7 +63,7 @@ REG32(IDR5, 0x14) > > #define SMMU_IDR5_OAS 4 > > -REG32(IIDR, 0x1c) > +REG32(IIDR, 0x18) > REG32(CR0, 0x20) > FIELD(CR0, SMMU_ENABLE, 0, 1) > FIELD(CR0, EVENTQEN, 2, 1) > -- Reviewed-by: Peter Maydell <peter.maydell@linaro.org> thanks -- PMM
diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h index 5babf72f7d..ef093eaff5 100644 --- a/hw/arm/smmuv3-internal.h +++ b/hw/arm/smmuv3-internal.h @@ -63,7 +63,7 @@ REG32(IDR5, 0x14) #define SMMU_IDR5_OAS 4 -REG32(IIDR, 0x1c) +REG32(IIDR, 0x18) REG32(CR0, 0x20) FIELD(CR0, SMMU_ENABLE, 0, 1) FIELD(CR0, EVENTQEN, 2, 1)
The SMMU IIDR register is at 0x018 offset. Signed-off-by: Eric Auger <eric.auger@redhat.com> Fixes: 10a83cb9887 ("hw/arm/smmuv3: Skeleton") --- hw/arm/smmuv3-internal.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)