[v2,2/2] clk: scmi: Fix min and max rate when registering clocks with discrete rates

Commit Message

Sudeep Holla July 9, 2020, 8:17 a.m. UTC

Currently we are not initializing the scmi clock with discrete rates
correctly. We fetch the min_rate and max_rate value only for clocks with
ranges and ignore the ones with discrete rates. This will lead to wrong
initialization of rate range when clock supports discrete rate.

Fix this by using the first and the last rate in the sorted list of the
discrete clock rates while registering the clock.

Link: https://lore.kernel.org/r/[e-mail]
Fixes: 6d6a1d82eaef7 ("clk: add support for clocks provided by SCMI")
Reported-by: Dien Pham <[e-mail]>
Signed-off-by: Sudeep Holla <[e-mail]>
---
 drivers/clk/clk-scmi.c | 22 +++++++++++++++++++---
 1 file changed, 19 insertions(+), 3 deletions(-)

Hi Stephen,

If you are fine, I can take this via ARM SoC along with the change in
firmware driver. However it is also fine if you want to merge this
independently as there is no strict dependency. Let me know either way.

v1[1]->v2:
	- Fixed the missing ; which was sent by mistake.

Regards,
Sudeep

[1] https://lore.kernel.org/r/[e-mail]

Comments

Dien Pham July 9, 2020, 8:26 a.m. UTC | #1

Hi Sudeep,

Thanks for your patch.

>-----Original Message-----
>From: Sudeep Holla <[e-mail]> 
>Sent: Thursday, July 9, 2020 3:17 PM
>To: [e-mail]; [e-mail]; Stephen Boyd <[e-mail]>
>Cc: Sudeep Holla <[e-mail]>; [e-mail]; Michael Turquette <[e-mail]>; Dien Pham <[e-mail]>
>Subject: [PATCH v2 2/2] clk: scmi: Fix min and max rate when registering clocks with discrete rates
>
>Currently we are not initializing the scmi clock with discrete rates correctly. We fetch the min_rate and max_rate value only for clocks with ranges and ignore the ones with discrete rates. This will lead to wrong initialization of rate range when clock supports discrete rate.
>
>Fix this by using the first and the last rate in the sorted list of the discrete clock rates while registering the clock.
>
>Link: https://lore.kernel.org/r/[e-mail]
>Fixes: 6d6a1d82eaef7 ("clk: add support for clocks provided by SCMI")
>Reported-by: Dien Pham <[e-mail]>
>Signed-off-by: Sudeep Holla <[e-mail]>
>---
> drivers/clk/clk-scmi.c | 22 +++++++++++++++++++---
> 1 file changed, 19 insertions(+), 3 deletions(-)
>
>Hi Stephen,
>
>If you are fine, I can take this via ARM SoC along with the change in firmware driver. However it is also fine if you want to merge this independently as there is no strict dependency. Let me know either way.
>
>v1[1]->v2:
>	- Fixed the missing ; which was sent by mistake.

I tested the patch,
I is ok and can fix my issue.

>Regards,
>Sudeep
>
>[1] https://lore.kernel.org/r/[e-mail]
>
>diff --git a/drivers/clk/clk-scmi.c b/drivers/clk/clk-scmi.c index c491f5de0f3f..c754dfbb73fd 100644
>--- a/drivers/clk/clk-scmi.c
>+++ b/drivers/clk/clk-scmi.c
>@@ -103,6 +103,8 @@ static const struct clk_ops scmi_clk_ops = {  static int scmi_clk_ops_init(struct device *dev, struct scmi_clk *sclk)  {
> 	int ret;
>+	unsigned long min_rate, max_rate;
>+
> 	struct clk_init_data init = {
> 		.flags = CLK_GET_RATE_NOCACHE,
> 		.num_parents = 0,
>@@ -112,9 +114,23 @@ static int scmi_clk_ops_init(struct device *dev, struct scmi_clk *sclk)
> 
> 	sclk->hw.init = &init;
> 	ret = devm_clk_hw_register(dev, &sclk->hw);
>-	if (!ret)
>-		clk_hw_set_rate_range(&sclk->hw, sclk->info->range.min_rate,
>-				      sclk->info->range.max_rate);
>+	if (ret)
>+		return ret;
>+
>+	if (sclk->info->rate_discrete) {
>+		int num_rates = sclk->info->list.num_rates;
>+
>+		if (num_rates <= 0)
>+			return -EINVAL;
>+
>+		min_rate = sclk->info->list.rates[0];
>+		max_rate = sclk->info->list.rates[num_rates - 1];
>+	} else {
>+		min_rate = sclk->info->range.min_rate;
>+		max_rate = sclk->info->range.max_rate;
>+	}
>+
>+	clk_hw_set_rate_range(&sclk->hw, min_rate, max_rate);
> 	return ret;
> }
> 
>--
>2.17.1

Best regard,
DIEN Pham

Sudeep Holla July 9, 2020, 8:39 a.m. UTC | #2

On Thu, Jul 09, 2020 at 08:26:54AM +0000, Dien Pham wrote:
> Hi Sudeep,
>
> Thanks for your patch.
>
> >-----Original Message-----
> >From: Sudeep Holla <[e-mail]>
> >Sent: Thursday, July 9, 2020 3:17 PM
> >To: [e-mail]; [e-mail]; Stephen Boyd <[e-mail]>
> >Cc: Sudeep Holla <[e-mail]>; [e-mail]; Michael Turquette <[e-mail]>; Dien Pham <[e-mail]>
> >Subject: [PATCH v2 2/2] clk: scmi: Fix min and max rate when registering clocks with discrete rates
> >
> >Currently we are not initializing the scmi clock with discrete rates correctly. We fetch the min_rate and max_rate value only for clocks with ranges and ignore the ones with discrete rates. This will lead to wrong initialization of rate range when clock supports discrete rate.
> >
> >Fix this by using the first and the last rate in the sorted list of the discrete clock rates while registering the clock.
> >
> >Link: https://lore.kernel.org/r/[e-mail]
> >Fixes: 6d6a1d82eaef7 ("clk: add support for clocks provided by SCMI")
> >Reported-by: Dien Pham <[e-mail]>
> >Signed-off-by: Sudeep Holla <[e-mail]>
> >---
> > drivers/clk/clk-scmi.c | 22 +++++++++++++++++++---
> > 1 file changed, 19 insertions(+), 3 deletions(-)
> >
> >Hi Stephen,
> >
> >If you are fine, I can take this via ARM SoC along with the change in firmware driver. However it is also fine if you want to merge this independently as there is no strict dependency. Let me know either way.
> >
> >v1[1]->v2:
> >	- Fixed the missing ; which was sent by mistake.
>
> I tested the patch,
> I is ok and can fix my issue.
>

Thanks for testing. Can I add ?

Tested-by: Dien Pham <[e-mail]>

--
Regards,
Sudeep

Dien Pham July 9, 2020, 8:55 a.m. UTC | #3

Dear Sudeep-san,

>-----Original Message-----
>From: Sudeep Holla <[e-mail]> 
>Sent: Thursday, July 9, 2020 3:39 PM
>To: Dien Pham <[e-mail]>
>Cc: [e-mail]; [e-mail]; Stephen Boyd <[e-mail]>; [e-mail]; Michael Turquette <[e-mail]>; Sudeep Holla <[e-mail]>
>Subject: Re: [PATCH v2 2/2] clk: scmi: Fix min and max rate when registering clocks with discrete rates
>
>On Thu, Jul 09, 2020 at 08:26:54AM +0000, Dien Pham wrote:
>> Hi Sudeep,
>>
>> Thanks for your patch.
>>
>> >-----Original Message-----
>> >From: Sudeep Holla <[e-mail]>
>> >Sent: Thursday, July 9, 2020 3:17 PM
>> >To: [e-mail]; [e-mail]; Stephen Boyd <[e-mail]>
>> >Cc: Sudeep Holla <[e-mail]>; [e-mail]; Michael Turquette <[e-mail]>; Dien Pham <[e-mail]>
>> >Subject: [PATCH v2 2/2] clk: scmi: Fix min and max rate when registering clocks with discrete rates
>> >
>> >Currently we are not initializing the scmi clock with discrete rates correctly. We fetch the min_rate and max_rate value only for clocks with ranges and ignore the ones with discrete rates. This will lead to wrong initialization of rate range when clock supports discrete rate.
>> >
>> >Fix this by using the first and the last rate in the sorted list of the discrete clock rates while registering the clock.
>> >
>> >Link: https://lore.kernel.org/r/[e-mail]
>> >Fixes: 6d6a1d82eaef7 ("clk: add support for clocks provided by SCMI")
>> >Reported-by: Dien Pham <[e-mail]>
>> >Signed-off-by: Sudeep Holla <[e-mail]>
>> >---
>> > drivers/clk/clk-scmi.c | 22 +++++++++++++++++++---
>> > 1 file changed, 19 insertions(+), 3 deletions(-)
>> >
>> >Hi Stephen,
>> >
>> >If you are fine, I can take this via ARM SoC along with the change in firmware driver. However it is also fine if you want to merge this independently as there is no strict dependency. Let me know either way.
>> >
>> >v1[1]->v2:
>> >	- Fixed the missing ; which was sent by mistake.
>>
>> I tested the patch,
>> I is ok and can fix my issue.
>>
>
>Thanks for testing. Can I add ?
>
>Tested-by: Dien Pham <[e-mail]>

It is ok.

Thanks,
Best regard,
DIEN Pham

Stephen Boyd July 10, 2020, 11:50 p.m. UTC | #4

Quoting Sudeep Holla (2020-07-09 01:17:05)
> Currently we are not initializing the scmi clock with discrete rates
> correctly. We fetch the min_rate and max_rate value only for clocks with
> ranges and ignore the ones with discrete rates. This will lead to wrong
> initialization of rate range when clock supports discrete rate.
> 
> Fix this by using the first and the last rate in the sorted list of the
> discrete clock rates while registering the clock.
> 
> Link: https://lore.kernel.org/r/[e-mail]
> Fixes: 6d6a1d82eaef7 ("clk: add support for clocks provided by SCMI")
> Reported-by: Dien Pham <[e-mail]>
> Signed-off-by: Sudeep Holla <[e-mail]>
> ---
>  drivers/clk/clk-scmi.c | 22 +++++++++++++++++++---
>  1 file changed, 19 insertions(+), 3 deletions(-)
> 
> Hi Stephen,
> 
> If you are fine, I can take this via ARM SoC along with the change in
> firmware driver. However it is also fine if you want to merge this
> independently as there is no strict dependency. Let me know either way.

I don't mind either way. If you want to send it in along with the
firmware change then that's fine.

Reviewed-by: Stephen Boyd <[e-mail]>

Sudeep Holla July 13, 2020, 1:21 p.m. UTC | #5

On Fri, Jul 10, 2020 at 04:50:40PM -0700, Stephen Boyd wrote:
> Quoting Sudeep Holla (2020-07-09 01:17:05)
> > Currently we are not initializing the scmi clock with discrete rates
> > correctly. We fetch the min_rate and max_rate value only for clocks with
> > ranges and ignore the ones with discrete rates. This will lead to wrong
> > initialization of rate range when clock supports discrete rate.
> > 
> > Fix this by using the first and the last rate in the sorted list of the
> > discrete clock rates while registering the clock.
> > 
> > Link: https://lore.kernel.org/r/[e-mail]
> > Fixes: 6d6a1d82eaef7 ("clk: add support for clocks provided by SCMI")
> > Reported-by: Dien Pham <[e-mail]>
> > Signed-off-by: Sudeep Holla <[e-mail]>
> > ---
> >  drivers/clk/clk-scmi.c | 22 +++++++++++++++++++---
> >  1 file changed, 19 insertions(+), 3 deletions(-)
> > 
> > Hi Stephen,
> > 
> > If you are fine, I can take this via ARM SoC along with the change in
> > firmware driver. However it is also fine if you want to merge this
> > independently as there is no strict dependency. Let me know either way.
> 
> I don't mind either way. If you want to send it in along with the
> firmware change then that's fine.
>

OK I have now queued and will send it to arm-soc.

> Reviewed-by: Stephen Boyd <[e-mail]>

Thanks for the review.

Patch

diff --git a/drivers/clk/clk-scmi.c b/drivers/clk/clk-scmi.c
index c491f5de0f3f..c754dfbb73fd 100644
--- a/drivers/clk/clk-scmi.c
+++ b/drivers/clk/clk-scmi.c
@@ -103,6 +103,8 @@  static const struct clk_ops scmi_clk_ops = {
 static int scmi_clk_ops_init(struct device *dev, struct scmi_clk *sclk)
 {
 	int ret;
+	unsigned long min_rate, max_rate;
+
 	struct clk_init_data init = {
 		.flags = CLK_GET_RATE_NOCACHE,
 		.num_parents = 0,
@@ -112,9 +114,23 @@  static int scmi_clk_ops_init(struct device *dev, struct scmi_clk *sclk)
 
 	sclk->hw.init = &init;
 	ret = devm_clk_hw_register(dev, &sclk->hw);
-	if (!ret)
-		clk_hw_set_rate_range(&sclk->hw, sclk->info->range.min_rate,
-				      sclk->info->range.max_rate);
+	if (ret)
+		return ret;
+
+	if (sclk->info->rate_discrete) {
+		int num_rates = sclk->info->list.num_rates;
+
+		if (num_rates <= 0)
+			return -EINVAL;
+
+		min_rate = sclk->info->list.rates[0];
+		max_rate = sclk->info->list.rates[num_rates - 1];
+	} else {
+		min_rate = sclk->info->range.min_rate;
+		max_rate = sclk->info->range.max_rate;
+	}
+
+	clk_hw_set_rate_range(&sclk->hw, min_rate, max_rate);
 	return ret;
 }