From patchwork Thu Jul 9 16:23:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Pierre-Louis Bossart X-Patchwork-Id: 11654711 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4E3C113B4 for ; Thu, 9 Jul 2020 16:29:05 +0000 (UTC) Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D96EF207DD for ; Thu, 9 Jul 2020 16:29:04 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=alsa-project.org header.i=@alsa-project.org header.b="TlU2DqGW" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D96EF207DD Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=alsa-devel-bounces@alsa-project.org Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id 6500B1607; Thu, 9 Jul 2020 18:28:15 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz 6500B1607 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1594312142; bh=ngblmSpQFUb22qF0BxjE67/HBTTcZTRukygKHx/x4s8=; h=From:To:Subject:Date:In-Reply-To:References:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=TlU2DqGWiGbTNhZsRk6Qyti7u26xr2wIHapPylMx677/OArVIV1l+hHoxViwb/7Od iBSK1zkbPQI+Rsk/1oKKLi9K8ULmh6LSvVZ1ULMrsiNmBL1IHIZK45df9nMH9fqnfX wBj4txPIedaiaMe0F51L0S98EHHz573KQH65Vll4= Received: from alsa1.perex.cz (localhost.localdomain [127.0.0.1]) by alsa1.perex.cz (Postfix) with ESMTP id A249FF802F7; Thu, 9 Jul 2020 18:24:24 +0200 (CEST) X-Original-To: alsa-devel@alsa-project.org Delivered-To: alsa-devel@alsa-project.org Received: by alsa1.perex.cz (Postfix, from userid 50401) id 73C88F802D2; Thu, 9 Jul 2020 18:24:14 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on alsa1.perex.cz X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE,URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id C14B4F80264 for ; Thu, 9 Jul 2020 18:23:58 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz C14B4F80264 IronPort-SDR: vcy7K6l3rJ118TVuAsW03Wc8718Nc20w+O3fFU2Z8kXKh29lkcZ81jtamBNgYis/iIS+97z9AE IycaUrnmueUA== X-IronPort-AV: E=McAfee;i="6000,8403,9677"; a="149515638" X-IronPort-AV: E=Sophos;i="5.75,331,1589266800"; d="scan'208";a="149515638" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jul 2020 09:23:54 -0700 IronPort-SDR: AFPU3/pslc3kyCCROQND6pvI376z8oj4lK+LEGNEsCaj+Gbv6jeU17N1negviMKydRse3Vvjbv jO3rlSgP7KAA== X-IronPort-AV: E=Sophos;i="5.75,331,1589266800"; d="scan'208";a="280353028" Received: from mdcoakle-mobl.amr.corp.intel.com (HELO pbossart-mobl3.amr.corp.intel.com) ([10.255.231.43]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jul 2020 09:23:53 -0700 From: Pierre-Louis Bossart To: alsa-devel@alsa-project.org Subject: [PATCH v4 06/10] ASoC: ux500: ux500_msp_i2s: Remove unused variables 'reg_val_DR' and 'reg_val_TSTDR' Date: Thu, 9 Jul 2020 11:23:23 -0500 Message-Id: <20200709162328.259586-7-pierre-louis.bossart@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200709162328.259586-1-pierre-louis.bossart@linux.intel.com> References: <20200709162328.259586-1-pierre-louis.bossart@linux.intel.com> MIME-Version: 1.0 Cc: Ola Lilja , tiwai@suse.de, Lee Jones , Takashi Iwai , Pierre-Louis Bossart , Liam Girdwood , Roger Nilsson , broonie@kernel.org, Sandeep Kaushik , zhong jiang , open list X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" From: Lee Jones Looks like these have been unchecked since the driver's inception in 2012. Fixes the following W=1 kernel build warning(s): sound/soc/ux500/ux500_msp_i2s.c: In function ‘flush_fifo_rx’: sound/soc/ux500/ux500_msp_i2s.c:398:6: warning: variable ‘reg_val_DR’ set but not used [-Wunused-but-set-variable] sound/soc/ux500/ux500_msp_i2s.c: In function ‘flush_fifo_tx’: sound/soc/ux500/ux500_msp_i2s.c:415:6: warning: variable ‘reg_val_TSTDR’ set but not used [-Wunused-but-set-variable] Cc: zhong jiang Cc: Ola Lilja Cc: Roger Nilsson Cc: Sandeep Kaushik Signed-off-by: Lee Jones Signed-off-by: Pierre-Louis Bossart --- sound/soc/ux500/ux500_msp_i2s.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/sound/soc/ux500/ux500_msp_i2s.c b/sound/soc/ux500/ux500_msp_i2s.c index 394d8b2a4a16..fd0b88bb7921 100644 --- a/sound/soc/ux500/ux500_msp_i2s.c +++ b/sound/soc/ux500/ux500_msp_i2s.c @@ -395,7 +395,7 @@ static int enable_msp(struct ux500_msp *msp, struct ux500_msp_config *config) static void flush_fifo_rx(struct ux500_msp *msp) { - u32 reg_val_DR, reg_val_GCR, reg_val_FLR; + u32 reg_val_GCR, reg_val_FLR; u32 limit = 32; reg_val_GCR = readl(msp->registers + MSP_GCR); @@ -403,7 +403,7 @@ static void flush_fifo_rx(struct ux500_msp *msp) reg_val_FLR = readl(msp->registers + MSP_FLR); while (!(reg_val_FLR & RX_FIFO_EMPTY) && limit--) { - reg_val_DR = readl(msp->registers + MSP_DR); + readl(msp->registers + MSP_DR); reg_val_FLR = readl(msp->registers + MSP_FLR); } @@ -412,7 +412,7 @@ static void flush_fifo_rx(struct ux500_msp *msp) static void flush_fifo_tx(struct ux500_msp *msp) { - u32 reg_val_TSTDR, reg_val_GCR, reg_val_FLR; + u32 reg_val_GCR, reg_val_FLR; u32 limit = 32; reg_val_GCR = readl(msp->registers + MSP_GCR); @@ -421,7 +421,7 @@ static void flush_fifo_tx(struct ux500_msp *msp) reg_val_FLR = readl(msp->registers + MSP_FLR); while (!(reg_val_FLR & TX_FIFO_EMPTY) && limit--) { - reg_val_TSTDR = readl(msp->registers + MSP_TSTDR); + readl(msp->registers + MSP_TSTDR); reg_val_FLR = readl(msp->registers + MSP_FLR); } writel(0x0, msp->registers + MSP_ITCR);