From patchwork Fri Jul 10 11:57:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthew Auld X-Patchwork-Id: 11656359 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 209216C1 for ; Fri, 10 Jul 2020 12:00:14 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 07FD52078D for ; Fri, 10 Jul 2020 12:00:14 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 07FD52078D Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1A67A6EBF5; Fri, 10 Jul 2020 12:00:07 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 51ECD6EBF9 for ; Fri, 10 Jul 2020 12:00:06 +0000 (UTC) IronPort-SDR: fJCIG4+jimmdOQ89mynMJdsLacr7zNpMIRtEYp7Fuz15iwSkZ4tlRKLhDip3ZQLgfy8SSa3QtF Jf63Nnl54Ifg== X-IronPort-AV: E=McAfee;i="6000,8403,9677"; a="149653729" X-IronPort-AV: E=Sophos;i="5.75,335,1589266800"; d="scan'208";a="149653729" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Jul 2020 05:00:06 -0700 IronPort-SDR: r6LGOjrMtu+gpavJUP9hl+bW+NfV58mz+xU8mLubzEY+6xQvtYRdq280jF4PBpiAMDffUwz7Jl xHwUTdrlEOvg== X-IronPort-AV: E=Sophos;i="5.75,335,1589266800"; d="scan'208";a="458257630" Received: from nmartino-mobl1.ger.corp.intel.com (HELO mwahaha-bdw.ger.corp.intel.com) ([10.255.207.224]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Jul 2020 05:00:03 -0700 From: Matthew Auld To: intel-gfx@lists.freedesktop.org Date: Fri, 10 Jul 2020 12:57:22 +0100 Message-Id: <20200710115757.290984-26-matthew.auld@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200710115757.290984-1-matthew.auld@intel.com> References: <20200710115757.290984-1-matthew.auld@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [RFC 25/60] drm/i915/dg1: Load DMC X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lucas De Marchi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Matt Atwood Add support to load DMC v2.0.2 on DG1 While we're at it, tweak the TGL and RKL firmware size definition to follow the convention used in previous platforms. Remove obsolete commenting. Bpec: 49230 Cc: Matt Roper Signed-off-by: Matt Atwood Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/display/intel_csr.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_csr.c b/drivers/gpu/drm/i915/display/intel_csr.c index f22a7645c249..ccf13ea627d7 100644 --- a/drivers/gpu/drm/i915/display/intel_csr.c +++ b/drivers/gpu/drm/i915/display/intel_csr.c @@ -38,15 +38,19 @@ * low-power state and comes back to normal. */ -#define GEN12_CSR_MAX_FW_SIZE ICL_CSR_MAX_FW_SIZE +#define DG1_CSR_PATH "i915/dg1_dmc_ver2_02.bin" +#define DG1_CSR_VERSION_REQUIRED CSR_VERSION(2, 2) +#define DG1_CSR_MAX_FW_SIZE ICL_CSR_MAX_FW_SIZE +MODULE_FIRMWARE(DG1_CSR_PATH); #define RKL_CSR_PATH "i915/rkl_dmc_ver2_01.bin" #define RKL_CSR_VERSION_REQUIRED CSR_VERSION(2, 1) +#define RKL_CSR_MAX_FW_SIZE ICL_CSR_MAX_FW_SIZE MODULE_FIRMWARE(RKL_CSR_PATH); #define TGL_CSR_PATH "i915/tgl_dmc_ver2_06.bin" #define TGL_CSR_VERSION_REQUIRED CSR_VERSION(2, 6) -#define TGL_CSR_MAX_FW_SIZE 0x6000 +#define TGL_CSR_MAX_FW_SIZE ICL_CSR_MAX_FW_SIZE MODULE_FIRMWARE(TGL_CSR_PATH); #define ICL_CSR_PATH "i915/icl_dmc_ver1_09.bin" @@ -686,15 +690,18 @@ void intel_csr_ucode_init(struct drm_i915_private *dev_priv) */ intel_csr_runtime_pm_get(dev_priv); - if (IS_ROCKETLAKE(dev_priv)) { + if (IS_DG1(dev_priv)) { + csr->fw_path = DG1_CSR_PATH; + csr->required_version = DG1_CSR_VERSION_REQUIRED; + csr->max_fw_size = DG1_CSR_MAX_FW_SIZE; + } else if (IS_ROCKETLAKE(dev_priv)) { csr->fw_path = RKL_CSR_PATH; csr->required_version = RKL_CSR_VERSION_REQUIRED; - csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE; + csr->max_fw_size = RKL_CSR_MAX_FW_SIZE; } else if (INTEL_GEN(dev_priv) >= 12) { csr->fw_path = TGL_CSR_PATH; csr->required_version = TGL_CSR_VERSION_REQUIRED; - /* Allow to load fw via parameter using the last known size */ - csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE; + csr->max_fw_size = TGL_CSR_MAX_FW_SIZE; } else if (IS_GEN(dev_priv, 11)) { csr->fw_path = ICL_CSR_PATH; csr->required_version = ICL_CSR_VERSION_REQUIRED;