| Message ID | 20200714003254.4044149-1-alistair.francis@wdc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Mon, Jul 13, 2020 at 5:43 PM Alistair Francis <alistair.francis@wdc.com> wrote: > > The following changes since commit 20c1df5476e1e9b5d3f5b94f9f3ce01d21f14c46: > > Merge remote-tracking branch 'remotes/kraxel/tags/fixes-20200713-pull-request' into staging (2020-07-13 16:58:44 +0100) > > are available in the Git repository at: > > git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20200713 > > for you to fetch changes up to cfad709bceb629a4ebeb5d8a3acd1871b9a6436b: > > target/riscv: Fix pmp NA4 implementation (2020-07-13 17:25:37 -0700) Sorry these are a little late, I was hoping to send them out last week but I was chasing down some bugs and waiting on a few patches. Alistair > > ---------------------------------------------------------------- > This is a colection of bug fixes and small imrprovements for RISC-V. > > This includes some vector extensions fixes, a PMP bug fix, OpenTitan > UART bug fix and support for OpenSBI dynamic firmware. > > ---------------------------------------------------------------- > Alexandre Mergnat (1): > target/riscv: Fix pmp NA4 implementation > > Alistair Francis (2): > hw/char: Convert the Ibex UART to use the qdev Clock model > hw/char: Convert the Ibex UART to use the registerfields API > > Atish Patra (4): > riscv: Unify Qemu's reset vector code path > RISC-V: Copy the fdt in dram instead of ROM > riscv: Add opensbi firmware dynamic support > RISC-V: Support 64 bit start address > > Bin Meng (3): > MAINTAINERS: Add an entry for OpenSBI firmware > hw/riscv: virt: Sort the SoC memmap table entries > hw/riscv: Modify MROM size to end at 0x10000 > > Frank Chang (4): > target/riscv: fix rsub gvec tcg_assert_listed_vecop assertion > target/riscv: correct the gvec IR called in gen_vec_rsub16_i64() > target/riscv: fix return value of do_opivx_widen() > target/riscv: fix vill bit index in vtype register > > Liao Pingfang (1): > tcg/riscv: Remove superfluous breaks > > include/hw/char/ibex_uart.h | 79 ++++++++-------- > include/hw/riscv/boot.h | 7 ++ > include/hw/riscv/boot_opensbi.h | 58 ++++++++++++ > target/riscv/cpu.h | 2 +- > hw/char/ibex_uart.c | 158 ++++++++++++++++++-------------- > hw/riscv/boot.c | 107 +++++++++++++++++++++ > hw/riscv/sifive_u.c | 53 ++++++----- > hw/riscv/spike.c | 59 ++++-------- > hw/riscv/virt.c | 63 ++++--------- > target/riscv/insn_trans/trans_rvv.inc.c | 9 +- > target/riscv/pmp.c | 2 +- > tcg/riscv/tcg-target.inc.c | 2 - > MAINTAINERS | 7 ++ > 13 files changed, 387 insertions(+), 219 deletions(-) > create mode 100644 include/hw/riscv/boot_opensbi.h >
On Tue, 14 Jul 2020 at 01:44, Alistair Francis <alistair.francis@wdc.com> wrote: > > The following changes since commit 20c1df5476e1e9b5d3f5b94f9f3ce01d21f14c46: > > Merge remote-tracking branch 'remotes/kraxel/tags/fixes-20200713-pull-request' into staging (2020-07-13 16:58:44 +0100) > > are available in the Git repository at: > > git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20200713 > > for you to fetch changes up to cfad709bceb629a4ebeb5d8a3acd1871b9a6436b: > > target/riscv: Fix pmp NA4 implementation (2020-07-13 17:25:37 -0700) > > ---------------------------------------------------------------- > This is a colection of bug fixes and small imrprovements for RISC-V. > > This includes some vector extensions fixes, a PMP bug fix, OpenTitan > UART bug fix and support for OpenSBI dynamic firmware. > > ---------------------------------------------------------------- Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/5.1 for any user-visible changes. -- PMM
The following changes since commit 20c1df5476e1e9b5d3f5b94f9f3ce01d21f14c46: Merge remote-tracking branch 'remotes/kraxel/tags/fixes-20200713-pull-request' into staging (2020-07-13 16:58:44 +0100) are available in the Git repository at: git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20200713 for you to fetch changes up to cfad709bceb629a4ebeb5d8a3acd1871b9a6436b: target/riscv: Fix pmp NA4 implementation (2020-07-13 17:25:37 -0700) ---------------------------------------------------------------- This is a colection of bug fixes and small imrprovements for RISC-V. This includes some vector extensions fixes, a PMP bug fix, OpenTitan UART bug fix and support for OpenSBI dynamic firmware. ---------------------------------------------------------------- Alexandre Mergnat (1): target/riscv: Fix pmp NA4 implementation Alistair Francis (2): hw/char: Convert the Ibex UART to use the qdev Clock model hw/char: Convert the Ibex UART to use the registerfields API Atish Patra (4): riscv: Unify Qemu's reset vector code path RISC-V: Copy the fdt in dram instead of ROM riscv: Add opensbi firmware dynamic support RISC-V: Support 64 bit start address Bin Meng (3): MAINTAINERS: Add an entry for OpenSBI firmware hw/riscv: virt: Sort the SoC memmap table entries hw/riscv: Modify MROM size to end at 0x10000 Frank Chang (4): target/riscv: fix rsub gvec tcg_assert_listed_vecop assertion target/riscv: correct the gvec IR called in gen_vec_rsub16_i64() target/riscv: fix return value of do_opivx_widen() target/riscv: fix vill bit index in vtype register Liao Pingfang (1): tcg/riscv: Remove superfluous breaks include/hw/char/ibex_uart.h | 79 ++++++++-------- include/hw/riscv/boot.h | 7 ++ include/hw/riscv/boot_opensbi.h | 58 ++++++++++++ target/riscv/cpu.h | 2 +- hw/char/ibex_uart.c | 158 ++++++++++++++++++-------------- hw/riscv/boot.c | 107 +++++++++++++++++++++ hw/riscv/sifive_u.c | 53 ++++++----- hw/riscv/spike.c | 59 ++++-------- hw/riscv/virt.c | 63 ++++--------- target/riscv/insn_trans/trans_rvv.inc.c | 9 +- target/riscv/pmp.c | 2 +- tcg/riscv/tcg-target.inc.c | 2 - MAINTAINERS | 7 ++ 13 files changed, 387 insertions(+), 219 deletions(-) create mode 100644 include/hw/riscv/boot_opensbi.h