[07/14] drm/i915: Sort HSW PCI IDs

Message ID	20200716172106.2656-8-ville.syrjala@linux.intel.com (mailing list archive)
State	New, archived
Headers	show Return-Path: <SRS0=YVpO=A3=lists.freedesktop.org=intel-gfx-bounces@kernel.org> DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org AD90820787 IronPort-SDR: RKCiBeenE5sb6xzRGg6IjHmN/2f+ZtV34Qugd3rm1cLts1HpOO6MRiIRrHH+p37e0w/X5kkfan 6ZRfTRS2zNTg== IronPort-SDR: 5F/aj2c8qH/fIj6MVqZR+Kp4ZfCWdnUcTrPrkKMGKgVr9i7pryN82vPVmqZ0KijtvbSr1uiw4p Rt4nSWJnhQPQ== From: Ville Syrjala <ville.syrjala@linux.intel.com> To: intel-gfx@lists.freedesktop.org Date: Thu, 16 Jul 2020 20:20:59 +0300 Message-Id: <20200716172106.2656-8-ville.syrjala@linux.intel.com> In-Reply-To: <20200716172106.2656-1-ville.syrjala@linux.intel.com> References: <20200716172106.2656-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 07/14] drm/i915: Sort HSW PCI IDs Precedence: list Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" <intel-gfx-bounces@lists.freedesktop.org>
Series	drm/i915: PCI ID cleanup \| expand [00/14] drm/i915: PCI ID cleanup [01/14] drm/i915: Update Haswell PCI IDs [02/14] drm/i915: Reclassify SKL 0x192a as GT3 [03/14] drm/i915: Reclassify SKL 0x1923 and 0x1927 as ULT [04/14] drm/i915: Add SKL GT1.5 PCI IDs [05/14] drm/i915: Try to fix the SKL GT3/4 vs. GT3e/4e comments [06/14] drm/i915: Ocd the HSW PCI ID hex numbers [07/14] drm/i915: Sort HSW PCI IDs [08/14] drm/i915: Sort SKL PCI IDs [09/14] drm/i915: Sort KBL PCI IDs [10/14] drm/i915: Sort CML PCI IDs [11/14] drm/i915: Sort CFL PCI IDs [12/14] drm/i915: Sort CNL PCI IDs [13/14] drm/i915: Sort ICL PCI IDs [14/14] drm/i915: Sort EHL/JSL PCI IDs

Message ID

20200716172106.2656-8-ville.syrjala@linux.intel.com (mailing list archive)

State

New, archived

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From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Date: Thu, 16 Jul 2020 20:20:59 +0300
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Subject: [Intel-gfx] [PATCH 07/14] drm/i915: Sort HSW PCI IDs
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Series

drm/i915: PCI ID cleanup | expand

Commit Message

Ville Syrjälä July 16, 2020, 5:20 p.m. UTC

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Sort the HSW PCI IDs numerically. Some order seems better than
randomness.

Cc: Alexei Podtelezhnikov <apodtele@gmail.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 include/drm/i915_pciids.h | 34 +++++++++++++++++-----------------
 1 file changed, 17 insertions(+), 17 deletions(-)

Comments

Srivatsa, Anusha Sept. 24, 2020, 12:44 a.m. UTC | #1

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: Thursday, July 16, 2020 10:21 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 07/14] drm/i915: Sort HSW PCI IDs
> 
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Sort the HSW PCI IDs numerically. Some order seems better than
> randomness.

I think the sorting, OCD-ness with hex and reclassifying can be combined in one patch.

Anusha 
> Cc: Alexei Podtelezhnikov <apodtele@gmail.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  include/drm/i915_pciids.h | 34 +++++++++++++++++-----------------
>  1 file changed, 17 insertions(+), 17 deletions(-)
> 
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h index
> 026db4d496e9..4870c3c9f9b2 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -170,9 +170,9 @@
> 
>  #define INTEL_HSW_ULT_GT1_IDS(info) \
>  	INTEL_VGA_DEVICE(0x0A02, info), /* ULT GT1 desktop */ \
> +	INTEL_VGA_DEVICE(0x0A06, info), /* ULT GT1 mobile */ \
>  	INTEL_VGA_DEVICE(0x0A0A, info), /* ULT GT1 server */ \
> -	INTEL_VGA_DEVICE(0x0A0B, info), /* ULT GT1 reserved */ \
> -	INTEL_VGA_DEVICE(0x0A06, info)  /* ULT GT1 mobile */
> +	INTEL_VGA_DEVICE(0x0A0B, info)  /* ULT GT1 reserved */
> 
>  #define INTEL_HSW_ULX_GT1_IDS(info) \
>  	INTEL_VGA_DEVICE(0x0A0E, info) /* ULX GT1 mobile */ @@ -181,26
> +181,26 @@
>  	INTEL_HSW_ULT_GT1_IDS(info), \
>  	INTEL_HSW_ULX_GT1_IDS(info), \
>  	INTEL_VGA_DEVICE(0x0402, info), /* GT1 desktop */ \
> +	INTEL_VGA_DEVICE(0x0406, info), /* GT1 mobile */ \
>  	INTEL_VGA_DEVICE(0x040A, info), /* GT1 server */ \
>  	INTEL_VGA_DEVICE(0x040B, info), /* GT1 reserved */ \
>  	INTEL_VGA_DEVICE(0x040E, info), /* GT1 reserved */ \
>  	INTEL_VGA_DEVICE(0x0C02, info), /* SDV GT1 desktop */ \
> +	INTEL_VGA_DEVICE(0x0C06, info), /* SDV GT1 mobile */ \
>  	INTEL_VGA_DEVICE(0x0C0A, info), /* SDV GT1 server */ \
>  	INTEL_VGA_DEVICE(0x0C0B, info), /* SDV GT1 reserved */ \
>  	INTEL_VGA_DEVICE(0x0C0E, info), /* SDV GT1 reserved */ \
>  	INTEL_VGA_DEVICE(0x0D02, info), /* CRW GT1 desktop */ \
> +	INTEL_VGA_DEVICE(0x0D06, info), /* CRW GT1 mobile */	\
>  	INTEL_VGA_DEVICE(0x0D0A, info), /* CRW GT1 server */ \
>  	INTEL_VGA_DEVICE(0x0D0B, info), /* CRW GT1 reserved */ \
> -	INTEL_VGA_DEVICE(0x0D0E, info), /* CRW GT1 reserved */ \
> -	INTEL_VGA_DEVICE(0x0406, info), /* GT1 mobile */ \
> -	INTEL_VGA_DEVICE(0x0C06, info), /* SDV GT1 mobile */ \
> -	INTEL_VGA_DEVICE(0x0D06, info)  /* CRW GT1 mobile */
> +	INTEL_VGA_DEVICE(0x0D0E, info)  /* CRW GT1 reserved */
> 
>  #define INTEL_HSW_ULT_GT2_IDS(info) \
>  	INTEL_VGA_DEVICE(0x0A12, info), /* ULT GT2 desktop */ \
> +	INTEL_VGA_DEVICE(0x0A16, info), /* ULT GT2 mobile */	\
>  	INTEL_VGA_DEVICE(0x0A1A, info), /* ULT GT2 server */ \
> -	INTEL_VGA_DEVICE(0x0A1B, info), /* ULT GT2 reserved */ \
> -	INTEL_VGA_DEVICE(0x0A16, info)  /* ULT GT2 mobile */
> +	INTEL_VGA_DEVICE(0x0A1B, info)  /* ULT GT2 reserved */ \
> 
>  #define INTEL_HSW_ULX_GT2_IDS(info) \
>  	INTEL_VGA_DEVICE(0x0A1E, info) /* ULX GT2 mobile */ \ @@ -
> 209,45 +209,45 @@
>  	INTEL_HSW_ULT_GT2_IDS(info), \
>  	INTEL_HSW_ULX_GT2_IDS(info), \
>  	INTEL_VGA_DEVICE(0x0412, info), /* GT2 desktop */ \
> +	INTEL_VGA_DEVICE(0x0416, info), /* GT2 mobile */ \
>  	INTEL_VGA_DEVICE(0x041A, info), /* GT2 server */ \
>  	INTEL_VGA_DEVICE(0x041B, info), /* GT2 reserved */ \
>  	INTEL_VGA_DEVICE(0x041E, info), /* GT2 reserved */ \
>  	INTEL_VGA_DEVICE(0x0C12, info), /* SDV GT2 desktop */ \
> +	INTEL_VGA_DEVICE(0x0C16, info), /* SDV GT2 mobile */ \
>  	INTEL_VGA_DEVICE(0x0C1A, info), /* SDV GT2 server */ \
>  	INTEL_VGA_DEVICE(0x0C1B, info), /* SDV GT2 reserved */ \
>  	INTEL_VGA_DEVICE(0x0C1E, info), /* SDV GT2 reserved */ \
>  	INTEL_VGA_DEVICE(0x0D12, info), /* CRW GT2 desktop */ \
> +	INTEL_VGA_DEVICE(0x0D16, info), /* CRW GT2 mobile */ \
>  	INTEL_VGA_DEVICE(0x0D1A, info), /* CRW GT2 server */ \
>  	INTEL_VGA_DEVICE(0x0D1B, info), /* CRW GT2 reserved */ \
> -	INTEL_VGA_DEVICE(0x0D1E, info), /* CRW GT2 reserved */ \
> -	INTEL_VGA_DEVICE(0x0416, info), /* GT2 mobile */ \
> -	INTEL_VGA_DEVICE(0x0C16, info), /* SDV GT2 mobile */ \
> -	INTEL_VGA_DEVICE(0x0D16, info)  /* CRW GT2 mobile */
> +	INTEL_VGA_DEVICE(0x0D1E, info)  /* CRW GT2 reserved */
> 
>  #define INTEL_HSW_ULT_GT3_IDS(info) \
>  	INTEL_VGA_DEVICE(0x0A22, info), /* ULT GT3 desktop */ \
> +	INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \
>  	INTEL_VGA_DEVICE(0x0A2A, info), /* ULT GT3 server */ \
>  	INTEL_VGA_DEVICE(0x0A2B, info), /* ULT GT3 reserved */ \
> -	INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \
>  	INTEL_VGA_DEVICE(0x0A2E, info)  /* ULT GT3 reserved */
> 
>  #define INTEL_HSW_GT3_IDS(info) \
>  	INTEL_HSW_ULT_GT3_IDS(info), \
>  	INTEL_VGA_DEVICE(0x0422, info), /* GT3 desktop */ \
> +	INTEL_VGA_DEVICE(0x0426, info), /* GT3 mobile */ \
>  	INTEL_VGA_DEVICE(0x042A, info), /* GT3 server */ \
>  	INTEL_VGA_DEVICE(0x042B, info), /* GT3 reserved */ \
>  	INTEL_VGA_DEVICE(0x042E, info), /* GT3 reserved */ \
>  	INTEL_VGA_DEVICE(0x0C22, info), /* SDV GT3 desktop */ \
> +	INTEL_VGA_DEVICE(0x0C26, info), /* SDV GT3 mobile */ \
>  	INTEL_VGA_DEVICE(0x0C2A, info), /* SDV GT3 server */ \
>  	INTEL_VGA_DEVICE(0x0C2B, info), /* SDV GT3 reserved */ \
>  	INTEL_VGA_DEVICE(0x0C2E, info), /* SDV GT3 reserved */ \
>  	INTEL_VGA_DEVICE(0x0D22, info), /* CRW GT3 desktop */ \
> +	INTEL_VGA_DEVICE(0x0D26, info), /* CRW GT3 mobile */ \
>  	INTEL_VGA_DEVICE(0x0D2A, info), /* CRW GT3 server */ \
>  	INTEL_VGA_DEVICE(0x0D2B, info), /* CRW GT3 reserved */ \
> -	INTEL_VGA_DEVICE(0x0D2E, info), /* CRW GT3 reserved */ \
> -	INTEL_VGA_DEVICE(0x0426, info), /* GT3 mobile */ \
> -	INTEL_VGA_DEVICE(0x0C26, info), /* SDV GT3 mobile */ \
> -	INTEL_VGA_DEVICE(0x0D26, info)  /* CRW GT3 mobile */
> +	INTEL_VGA_DEVICE(0x0D2E, info)  /* CRW GT3 reserved */
> 
>  #define INTEL_HSW_IDS(info) \
>  	INTEL_HSW_GT1_IDS(info), \
> --
> 2.26.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 026db4d496e9..4870c3c9f9b2 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -170,9 +170,9 @@ 
 
 #define INTEL_HSW_ULT_GT1_IDS(info) \
 	INTEL_VGA_DEVICE(0x0A02, info), /* ULT GT1 desktop */ \
+	INTEL_VGA_DEVICE(0x0A06, info), /* ULT GT1 mobile */ \
 	INTEL_VGA_DEVICE(0x0A0A, info), /* ULT GT1 server */ \
-	INTEL_VGA_DEVICE(0x0A0B, info), /* ULT GT1 reserved */ \
-	INTEL_VGA_DEVICE(0x0A06, info)  /* ULT GT1 mobile */
+	INTEL_VGA_DEVICE(0x0A0B, info)  /* ULT GT1 reserved */
 
 #define INTEL_HSW_ULX_GT1_IDS(info) \
 	INTEL_VGA_DEVICE(0x0A0E, info) /* ULX GT1 mobile */
@@ -181,26 +181,26 @@ 
 	INTEL_HSW_ULT_GT1_IDS(info), \
 	INTEL_HSW_ULX_GT1_IDS(info), \
 	INTEL_VGA_DEVICE(0x0402, info), /* GT1 desktop */ \
+	INTEL_VGA_DEVICE(0x0406, info), /* GT1 mobile */ \
 	INTEL_VGA_DEVICE(0x040A, info), /* GT1 server */ \
 	INTEL_VGA_DEVICE(0x040B, info), /* GT1 reserved */ \
 	INTEL_VGA_DEVICE(0x040E, info), /* GT1 reserved */ \
 	INTEL_VGA_DEVICE(0x0C02, info), /* SDV GT1 desktop */ \
+	INTEL_VGA_DEVICE(0x0C06, info), /* SDV GT1 mobile */ \
 	INTEL_VGA_DEVICE(0x0C0A, info), /* SDV GT1 server */ \
 	INTEL_VGA_DEVICE(0x0C0B, info), /* SDV GT1 reserved */ \
 	INTEL_VGA_DEVICE(0x0C0E, info), /* SDV GT1 reserved */ \
 	INTEL_VGA_DEVICE(0x0D02, info), /* CRW GT1 desktop */ \
+	INTEL_VGA_DEVICE(0x0D06, info), /* CRW GT1 mobile */	\
 	INTEL_VGA_DEVICE(0x0D0A, info), /* CRW GT1 server */ \
 	INTEL_VGA_DEVICE(0x0D0B, info), /* CRW GT1 reserved */ \
-	INTEL_VGA_DEVICE(0x0D0E, info), /* CRW GT1 reserved */ \
-	INTEL_VGA_DEVICE(0x0406, info), /* GT1 mobile */ \
-	INTEL_VGA_DEVICE(0x0C06, info), /* SDV GT1 mobile */ \
-	INTEL_VGA_DEVICE(0x0D06, info)  /* CRW GT1 mobile */
+	INTEL_VGA_DEVICE(0x0D0E, info)  /* CRW GT1 reserved */
 
 #define INTEL_HSW_ULT_GT2_IDS(info) \
 	INTEL_VGA_DEVICE(0x0A12, info), /* ULT GT2 desktop */ \
+	INTEL_VGA_DEVICE(0x0A16, info), /* ULT GT2 mobile */	\
 	INTEL_VGA_DEVICE(0x0A1A, info), /* ULT GT2 server */ \
-	INTEL_VGA_DEVICE(0x0A1B, info), /* ULT GT2 reserved */ \
-	INTEL_VGA_DEVICE(0x0A16, info)  /* ULT GT2 mobile */
+	INTEL_VGA_DEVICE(0x0A1B, info)  /* ULT GT2 reserved */ \
 
 #define INTEL_HSW_ULX_GT2_IDS(info) \
 	INTEL_VGA_DEVICE(0x0A1E, info) /* ULX GT2 mobile */ \
@@ -209,45 +209,45 @@ 
 	INTEL_HSW_ULT_GT2_IDS(info), \
 	INTEL_HSW_ULX_GT2_IDS(info), \
 	INTEL_VGA_DEVICE(0x0412, info), /* GT2 desktop */ \
+	INTEL_VGA_DEVICE(0x0416, info), /* GT2 mobile */ \
 	INTEL_VGA_DEVICE(0x041A, info), /* GT2 server */ \
 	INTEL_VGA_DEVICE(0x041B, info), /* GT2 reserved */ \
 	INTEL_VGA_DEVICE(0x041E, info), /* GT2 reserved */ \
 	INTEL_VGA_DEVICE(0x0C12, info), /* SDV GT2 desktop */ \
+	INTEL_VGA_DEVICE(0x0C16, info), /* SDV GT2 mobile */ \
 	INTEL_VGA_DEVICE(0x0C1A, info), /* SDV GT2 server */ \
 	INTEL_VGA_DEVICE(0x0C1B, info), /* SDV GT2 reserved */ \
 	INTEL_VGA_DEVICE(0x0C1E, info), /* SDV GT2 reserved */ \
 	INTEL_VGA_DEVICE(0x0D12, info), /* CRW GT2 desktop */ \
+	INTEL_VGA_DEVICE(0x0D16, info), /* CRW GT2 mobile */ \
 	INTEL_VGA_DEVICE(0x0D1A, info), /* CRW GT2 server */ \
 	INTEL_VGA_DEVICE(0x0D1B, info), /* CRW GT2 reserved */ \
-	INTEL_VGA_DEVICE(0x0D1E, info), /* CRW GT2 reserved */ \
-	INTEL_VGA_DEVICE(0x0416, info), /* GT2 mobile */ \
-	INTEL_VGA_DEVICE(0x0C16, info), /* SDV GT2 mobile */ \
-	INTEL_VGA_DEVICE(0x0D16, info)  /* CRW GT2 mobile */
+	INTEL_VGA_DEVICE(0x0D1E, info)  /* CRW GT2 reserved */
 
 #define INTEL_HSW_ULT_GT3_IDS(info) \
 	INTEL_VGA_DEVICE(0x0A22, info), /* ULT GT3 desktop */ \
+	INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \
 	INTEL_VGA_DEVICE(0x0A2A, info), /* ULT GT3 server */ \
 	INTEL_VGA_DEVICE(0x0A2B, info), /* ULT GT3 reserved */ \
-	INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \
 	INTEL_VGA_DEVICE(0x0A2E, info)  /* ULT GT3 reserved */
 
 #define INTEL_HSW_GT3_IDS(info) \
 	INTEL_HSW_ULT_GT3_IDS(info), \
 	INTEL_VGA_DEVICE(0x0422, info), /* GT3 desktop */ \
+	INTEL_VGA_DEVICE(0x0426, info), /* GT3 mobile */ \
 	INTEL_VGA_DEVICE(0x042A, info), /* GT3 server */ \
 	INTEL_VGA_DEVICE(0x042B, info), /* GT3 reserved */ \
 	INTEL_VGA_DEVICE(0x042E, info), /* GT3 reserved */ \
 	INTEL_VGA_DEVICE(0x0C22, info), /* SDV GT3 desktop */ \
+	INTEL_VGA_DEVICE(0x0C26, info), /* SDV GT3 mobile */ \
 	INTEL_VGA_DEVICE(0x0C2A, info), /* SDV GT3 server */ \
 	INTEL_VGA_DEVICE(0x0C2B, info), /* SDV GT3 reserved */ \
 	INTEL_VGA_DEVICE(0x0C2E, info), /* SDV GT3 reserved */ \
 	INTEL_VGA_DEVICE(0x0D22, info), /* CRW GT3 desktop */ \
+	INTEL_VGA_DEVICE(0x0D26, info), /* CRW GT3 mobile */ \
 	INTEL_VGA_DEVICE(0x0D2A, info), /* CRW GT3 server */ \
 	INTEL_VGA_DEVICE(0x0D2B, info), /* CRW GT3 reserved */ \
-	INTEL_VGA_DEVICE(0x0D2E, info), /* CRW GT3 reserved */ \
-	INTEL_VGA_DEVICE(0x0426, info), /* GT3 mobile */ \
-	INTEL_VGA_DEVICE(0x0C26, info), /* SDV GT3 mobile */ \
-	INTEL_VGA_DEVICE(0x0D26, info)  /* CRW GT3 mobile */
+	INTEL_VGA_DEVICE(0x0D2E, info)  /* CRW GT3 reserved */
 
 #define INTEL_HSW_IDS(info) \
 	INTEL_HSW_GT1_IDS(info), \

[07/14] drm/i915: Sort HSW PCI IDs

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