From patchwork Fri Jul 17 21:13:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 11671215 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 98B0913B1 for ; Fri, 17 Jul 2020 21:14:28 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 816E520717 for ; Fri, 17 Jul 2020 21:14:28 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 816E520717 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1E1516E233; Fri, 17 Jul 2020 21:14:27 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9578E6E1F8 for ; Fri, 17 Jul 2020 21:14:25 +0000 (UTC) IronPort-SDR: XMTOBSlKFze5n6JPr6YrQiavGgHpyd17YIAlRDDTl+rQr2dSI5tNrtb024ksV09pU16LpVgvPm HeX+VvuVaz7A== X-IronPort-AV: E=McAfee;i="6000,8403,9685"; a="147652422" X-IronPort-AV: E=Sophos;i="5.75,364,1589266800"; d="scan'208";a="147652422" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jul 2020 14:14:25 -0700 IronPort-SDR: R9lbweByiSRI8XlrC+p4GB1klBDe6FmtAVSvwm8kmJItO3pvafpPcMX0A/YEHU4iefnjDkH3RP goxaIQQk57wQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.75,364,1589266800"; d="scan'208";a="269624839" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.174]) by fmsmga007.fm.intel.com with SMTP; 17 Jul 2020 14:14:23 -0700 Received: by stinkbox (sSMTP sendmail emulation); Sat, 18 Jul 2020 00:14:22 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Sat, 18 Jul 2020 00:13:38 +0300 Message-Id: <20200717211345.26851-14-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200717211345.26851-1-ville.syrjala@linux.intel.com> References: <20200717211345.26851-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 13/20] drm/i915: Add gamma/degamm readout for ivb/hsw X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä We now have all the code necessary for gamma/degamma readout on ivb/hsw. Plug it all in. Signed-off-by: Ville Syrjälä Reviewed-by: Uma Shankar --- drivers/gpu/drm/i915/display/intel_color.c | 32 ++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index 9f01fb316efa..886f3f0d873a 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -1999,6 +1999,37 @@ static struct drm_property_blob *ivb_read_lut_10(struct intel_crtc *crtc, return blob; } +static void ivb_read_luts(struct intel_crtc_state *crtc_state) +{ + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + struct drm_property_blob **blob = + crtc_state->csc_mode & CSC_POSITION_BEFORE_GAMMA ? + &crtc_state->hw.gamma_lut : &crtc_state->hw.degamma_lut; + + if (!crtc_state->gamma_enable) + return; + + switch (crtc_state->gamma_mode) { + case GAMMA_MODE_MODE_8BIT: + *blob = ilk_read_lut_8(crtc); + break; + case GAMMA_MODE_MODE_SPLIT: + crtc_state->hw.degamma_lut = + ivb_read_lut_10(crtc, PAL_PREC_SPLIT_MODE | + PAL_PREC_INDEX_VALUE(0)); + crtc_state->hw.gamma_lut = + ivb_read_lut_10(crtc, PAL_PREC_SPLIT_MODE | + PAL_PREC_INDEX_VALUE(512)); + break; + case GAMMA_MODE_MODE_10BIT: + *blob = ivb_read_lut_10(crtc, PAL_PREC_INDEX_VALUE(0)); + break; + default: + MISSING_CASE(crtc_state->gamma_mode); + break; + } +} + /* On BDW+ the index auto increment mode actually works */ static struct drm_property_blob *bdw_read_lut_10(struct intel_crtc *crtc, u32 prec_index) @@ -2236,6 +2267,7 @@ void intel_color_init(struct intel_crtc *crtc) dev_priv->display.read_luts = bdw_read_luts; } else if (INTEL_GEN(dev_priv) >= 7) { dev_priv->display.load_luts = ivb_load_luts; + dev_priv->display.read_luts = ivb_read_luts; } else { dev_priv->display.load_luts = ilk_load_luts; dev_priv->display.read_luts = ilk_read_luts;