| Message ID | 20200723221021.40456-1-jose.souza@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915: Implement WA 14011294188 | expand |
On Thu, Jul 23, 2020 at 03:10:21PM -0700, José Roberto de Souza wrote: > Although the WA description targets the platforms it is a workaround > for the affected PCHs, that is why it is being checked. > > BSpec: 52890 > BSpec: 53273 > BSpec: 52888 > Signed-off-by: José Roberto de Souza <jose.souza@intel.com> > --- > drivers/gpu/drm/i915/display/intel_display_power.c | 5 +++++ > drivers/gpu/drm/i915/i915_reg.h | 1 + > 2 files changed, 6 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c > index 0c713e83274d..3efb3d6e4474 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_power.c > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c > @@ -5302,6 +5302,11 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv, > > gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); > > + /* Wa_14011294188:ehl,jsl,tgl,rkl */ > + if (INTEL_PCH_TYPE(dev_priv) >= PCH_JSP) I think we also want an "&& INTEL_PCH_TYPE < PCH_DG1" here to exclude "fake" PCH's. Aside from that, Reviewed-by: Matt Roper <matthew.d.roper@intel.com> > + intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D, 0, > + PCH_DPMGUNIT_CLOCK_GATE_DISABLE); > + > /* 1. Enable PCH reset handshake. */ > intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv)); > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index a0d31f3bf634..5eae593ee784 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -8730,6 +8730,7 @@ enum { > #define PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 31) > #define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1 << 30) > #define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1 << 29) > +#define PCH_DPMGUNIT_CLOCK_GATE_DISABLE (1 << 15) > #define PCH_CPUNIT_CLOCK_GATE_DISABLE (1 << 14) > #define CNP_PWM_CGE_GATING_DISABLE (1 << 13) > #define PCH_LP_PARTITION_LEVEL_DISABLE (1 << 12) > -- > 2.27.0 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 0c713e83274d..3efb3d6e4474 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -5302,6 +5302,11 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv, gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); + /* Wa_14011294188:ehl,jsl,tgl,rkl */ + if (INTEL_PCH_TYPE(dev_priv) >= PCH_JSP) + intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D, 0, + PCH_DPMGUNIT_CLOCK_GATE_DISABLE); + /* 1. Enable PCH reset handshake. */ intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv)); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index a0d31f3bf634..5eae593ee784 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -8730,6 +8730,7 @@ enum { #define PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 31) #define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1 << 30) #define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1 << 29) +#define PCH_DPMGUNIT_CLOCK_GATE_DISABLE (1 << 15) #define PCH_CPUNIT_CLOCK_GATE_DISABLE (1 << 14) #define CNP_PWM_CGE_GATING_DISABLE (1 << 13) #define PCH_LP_PARTITION_LEVEL_DISABLE (1 << 12)
Although the WA description targets the platforms it is a workaround for the affected PCHs, that is why it is being checked. BSpec: 52890 BSpec: 53273 BSpec: 52888 Signed-off-by: José Roberto de Souza <jose.souza@intel.com> --- drivers/gpu/drm/i915/display/intel_display_power.c | 5 +++++ drivers/gpu/drm/i915/i915_reg.h | 1 + 2 files changed, 6 insertions(+)