| Message ID | 1596115816-11758-4-git-send-email-hanks.chen@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add basic SoC Support for Mediatek MT6779 SoC | expand |
Hi all, Gentle ping on this patch. Thanks Hanks Chen On Thu, 2020-07-30 at 21:30 +0800, Hanks Chen wrote: > Add MT6779 UART0 clock support. > > Fixes: 710774e04861 ("clk: mediatek: Add MT6779 clock support") > Signed-off-by: Wendell Lin <wendell.lin@mediatek.com> > Signed-off-by: Hanks Chen <hanks.chen@mediatek.com> > Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> > --- > drivers/clk/mediatek/clk-mt6779.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/clk/mediatek/clk-mt6779.c b/drivers/clk/mediatek/clk-mt6779.c > index 9766cccf5844..6e0d3a166729 100644 > --- a/drivers/clk/mediatek/clk-mt6779.c > +++ b/drivers/clk/mediatek/clk-mt6779.c > @@ -919,6 +919,8 @@ static const struct mtk_gate infra_clks[] = { > "pwm_sel", 19), > GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm", > "pwm_sel", 21), > + GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0", > + "uart_sel", 22), > GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1", > "uart_sel", 23), > GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2",
Hi Michael & Stephen, Please kindly let me know your comments about this patch. Thanks Regards, Hanks On Tue, 2020-09-08 at 14:25 +0800, Hanks Chen wrote: > Hi all, > > Gentle ping on this patch. > > Thanks > > > Hanks Chen > > > On Thu, 2020-07-30 at 21:30 +0800, Hanks Chen wrote: > > Add MT6779 UART0 clock support. > > > > Fixes: 710774e04861 ("clk: mediatek: Add MT6779 clock support") > > Signed-off-by: Wendell Lin <wendell.lin@mediatek.com> > > Signed-off-by: Hanks Chen <hanks.chen@mediatek.com> > > Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> > > --- > > drivers/clk/mediatek/clk-mt6779.c | 2 ++ > > 1 file changed, 2 insertions(+) > > > > diff --git a/drivers/clk/mediatek/clk-mt6779.c b/drivers/clk/mediatek/clk-mt6779.c > > index 9766cccf5844..6e0d3a166729 100644 > > --- a/drivers/clk/mediatek/clk-mt6779.c > > +++ b/drivers/clk/mediatek/clk-mt6779.c > > @@ -919,6 +919,8 @@ static const struct mtk_gate infra_clks[] = { > > "pwm_sel", 19), > > GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm", > > "pwm_sel", 21), > > + GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0", > > + "uart_sel", 22), > > GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1", > > "uart_sel", 23), > > GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2", > > _______________________________________________ > Linux-mediatek mailing list > Linux-mediatek@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-mediatek
Quoting Hanks Chen (2020-10-03 03:06:47) > Hi Michael & Stephen, > > Please kindly let me know your comments about this patch. > Thanks > What's the base for this patch? I tried applying to v5.9-rc1 and it didn't work.
On Wed, 2020-10-07 at 19:00 -0700, Stephen Boyd wrote: > Quoting Hanks Chen (2020-10-03 03:06:47) > > Hi Michael & Stephen, > > > > Please kindly let me know your comments about this patch. > > Thanks > > > > What's the base for this patch? I tried applying to v5.9-rc1 and it > didn't work. Sorry, what does that mean? Do you have encountered a merged conflict or run time failed? I based on kernel-5.8-rc1 to add it and it can boot to kernel shell. Thanks! Hanks Chen
Hi Stephen, On 08/10/2020 04:00, Stephen Boyd wrote: > Quoting Hanks Chen (2020-10-03 03:06:47) >> Hi Michael & Stephen, >> >> Please kindly let me know your comments about this patch. >> Thanks >> > > What's the base for this patch? I tried applying to v5.9-rc1 and it > didn't work. > Can you please double check. The file the patch touches didn't get touched since v5.5-rc1. I tried to apply it and it didn't give me any error. I paste my way of applying patches just in case: b4.sh am -l -o /tmp -n patch -P 3 1596115816-11758-4-git-send-email-hanks.chen@mediatek.com && git am -3 -s /tmp/patch.mbx Regards, Matthias
Quoting Hanks Chen (2020-10-07 19:39:13) > On Wed, 2020-10-07 at 19:00 -0700, Stephen Boyd wrote: > > Quoting Hanks Chen (2020-10-03 03:06:47) > > > Hi Michael & Stephen, > > > > > > Please kindly let me know your comments about this patch. > > > Thanks > > > > > > > What's the base for this patch? I tried applying to v5.9-rc1 and it > > didn't work. > > Sorry, what does that mean? > > Do you have encountered a merged conflict or run time failed? > > I based on kernel-5.8-rc1 to add it and it can boot to kernel shell. > Ah I see what it is. The email isn't actually plain text, it is base64 encoded and so git am gets confused by the CRLF line endings that are encoded in there. Any chance you can send patches in actual plain text format in the future?
Quoting Hanks Chen (2020-07-30 06:30:16) > Add MT6779 UART0 clock support. > > Fixes: 710774e04861 ("clk: mediatek: Add MT6779 clock support") > Signed-off-by: Wendell Lin <wendell.lin@mediatek.com> > Signed-off-by: Hanks Chen <hanks.chen@mediatek.com> > Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> > --- Applied to clk-next
diff --git a/drivers/clk/mediatek/clk-mt6779.c b/drivers/clk/mediatek/clk-mt6779.c index 9766cccf5844..6e0d3a166729 100644 --- a/drivers/clk/mediatek/clk-mt6779.c +++ b/drivers/clk/mediatek/clk-mt6779.c @@ -919,6 +919,8 @@ static const struct mtk_gate infra_clks[] = { "pwm_sel", 19), GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm", "pwm_sel", 21), + GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0", + "uart_sel", 22), GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1", "uart_sel", 23), GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2",
Add MT6779 UART0 clock support. Fixes: 710774e04861 ("clk: mediatek: Add MT6779 clock support") Signed-off-by: Wendell Lin <wendell.lin@mediatek.com> Signed-off-by: Hanks Chen <hanks.chen@mediatek.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> --- drivers/clk/mediatek/clk-mt6779.c | 2 ++ 1 file changed, 2 insertions(+)