From patchwork Mon Aug 3 13:40:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "liuqi (BA)" X-Patchwork-Id: 11698157 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2F7F91575 for ; Mon, 3 Aug 2020 13:42:03 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id F31D92076E for ; Mon, 3 Aug 2020 13:42:02 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="FjdTnFDV" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org F31D92076E Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=huawei.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:To:From: Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender :Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Owner; bh=CIo2mGXKOuABseafpOE0CUA+Zcapnlev/uROsFXRrUM=; b=FjdTnFDVxx3PtRVp403l2uhF3j btPwV0CAS6/olaHY9Tcdc/M56t7e+z73EtqyzG2WeqpMhWizrwu1hQsPUb3f93jEffFLZIfT5Oqr0 P7XMforMOnRseFzjw6K3DtfRI3LWCLfj7vIWhUmQNAwMmRjJpO1maZcfWSnAwGRHQ3BMoll7rBq+u u5IR//WTtGk55gH4OL88FfqDkVfHylqSh0006jtvmVje6bTMty28aNi7q6xjh3EsfKr0SRpFSy+zA gSqyVSJL6q0/7e32LjHagU5LZMm2w5oDuTwsnRH9E2DuPi/rDqm4aZdocjb55VJ20RZELe0UloCPT 51+YYuHw==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1k2aiq-0005zS-Gx; Mon, 03 Aug 2020 13:41:48 +0000 Received: from szxga06-in.huawei.com ([45.249.212.32] helo=huawei.com) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1k2ain-0005yc-JR for linux-arm-kernel@lists.infradead.org; Mon, 03 Aug 2020 13:41:46 +0000 Received: from DGGEMS403-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 8313DBA214502E009910; Mon, 3 Aug 2020 21:41:40 +0800 (CST) Received: from localhost.localdomain (10.67.165.24) by DGGEMS403-HUB.china.huawei.com (10.3.19.203) with Microsoft SMTP Server id 14.3.487.0; Mon, 3 Aug 2020 21:41:30 +0800 From: Qi Liu To: , , Subject: [PATCH] coresight: etm4x: Modify core-commit of cpu to avoid the overflow of HiSilicon ETM Date: Mon, 3 Aug 2020 21:40:42 +0800 Message-ID: <1596462042-28026-1-git-send-email-liuqi115@huawei.com> X-Mailer: git-send-email 2.8.1 MIME-Version: 1.0 X-Originating-IP: [10.67.165.24] X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200803_094145_910412_F279EA68 X-CRM114-Status: GOOD ( 12.87 ) X-Spam-Score: -2.3 (--) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-2.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [45.249.212.32 listed in list.dnswl.org] -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.0 SPF_PASS SPF: sender matches SPF record 0.0 RCVD_IN_MSPIKE_H4 RBL: Very Good reputation (+4) [45.249.212.32 listed in wl.mailspike.net] 0.0 RCVD_IN_MSPIKE_WL Mailspike good senders X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linuxarm@huawei.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org When too much trace information is generated on-chip, the ETM will overflow, and may cause data loss. This is a common phenomenon on ETM devices. But sometimes we do not want to lose any performance trace data, so we suppress the speed of instructions sent from CPU core to ETM to avoid the overflow of ETM. Signed-off-by: Qi Liu --- drivers/hwtracing/coresight/coresight-etm4x.c | 46 +++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) -- 2.8.1 diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index 4a4f0bd..ca9fb11 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -43,6 +43,11 @@ MODULE_PARM_DESC(boot_enable, "Enable tracing on boot"); #define PARAM_PM_SAVE_NEVER 1 /* never save any state */ #define PARAM_PM_SAVE_SELF_HOSTED 2 /* save self-hosted state only */ +#define CORE_COMMIT_CLEAR 0x3000 +#define CORE_COMMIT_SHIFT 12 +#define HISI_ETM_AMBA_ID_V1 0x000b6d01 +#define HISI_ETM_AMBA_ID_V2 0x000b6d02 + static int pm_save_enable = PARAM_PM_SAVE_FIRMWARE; module_param(pm_save_enable, int, 0444); MODULE_PARM_DESC(pm_save_enable, @@ -104,11 +109,41 @@ struct etm4_enable_arg { int rc; }; +static void etm4_cpu_actlr1_cfg(void *info) +{ + struct etm4_enable_arg *arg = (struct etm4_enable_arg *)info; + u64 val; + + asm volatile("mrs %0,s3_1_c15_c2_5" : "=r"(val)); + val &= ~CORE_COMMIT_CLEAR; + val |= arg->rc << CORE_COMMIT_SHIFT; + asm volatile("msr s3_1_c15_c2_5,%0" : : "r"(val)); +} + +static void etm4_config_core_commit(int cpu, int val) +{ + struct etm4_enable_arg arg = {0}; + + arg.rc = val; + smp_call_function_single(cpu, etm4_cpu_actlr1_cfg, &arg, 1); +} + static int etm4_enable_hw(struct etmv4_drvdata *drvdata) { int i, rc; + struct amba_device *adev; struct etmv4_config *config = &drvdata->config; struct device *etm_dev = &drvdata->csdev->dev; + struct device *dev = drvdata->csdev->dev.parent; + + adev = container_of(dev, struct amba_device, dev); + /* + * If ETM device is HiSilicon ETM device, reduce the + * core-commit to avoid ETM overflow. + */ + if (adev->periphid == HISI_ETM_AMBA_ID_V1 || + adev->periphid == HISI_ETM_AMBA_ID_V2) + etm4_config_core_commit(drvdata->cpu, 1); CS_UNLOCK(drvdata->base); @@ -469,11 +504,22 @@ static int etm4_enable(struct coresight_device *csdev, static void etm4_disable_hw(void *info) { u32 control; + struct amba_device *adev; struct etmv4_drvdata *drvdata = info; struct etmv4_config *config = &drvdata->config; struct device *etm_dev = &drvdata->csdev->dev; + struct device *dev = drvdata->csdev->dev.parent; int i; + adev = container_of(dev, struct amba_device, dev); + /* + * If ETM device is HiSilicon ETM device, resume the + * core-commit after ETM trace is complete. + */ + if (adev->periphid == HISI_ETM_AMBA_ID_V1 || + adev->periphid == HISI_ETM_AMBA_ID_V2) + etm4_config_core_commit(drvdata->cpu, 0); + CS_UNLOCK(drvdata->base); /* power can be removed from the trace unit now */