[6/8] drm/amd/display: Set DC options from modifiers.
diff mbox series

Message ID 20200804213119.25091-7-bas@basnieuwenhuizen.nl
State New
Headers show
Series
  • amd/display: Add GFX9+ modifier support.
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Commit Message

Bas Nieuwenhuizen Aug. 4, 2020, 9:31 p.m. UTC
This sets the DC tiling options from the modifier, if modifiers
are used for the FB. This patch by itself does not expose the
support yet though.

There is not much validation yet to limit the scope of this
patch, but the current validation is at the same level as
the BO metadata path.

Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 109 +++++++++++++++++-
 1 file changed, 103 insertions(+), 6 deletions(-)

Comments

Daniel Vetter Aug. 5, 2020, 7:32 a.m. UTC | #1
On Tue, Aug 04, 2020 at 11:31:17PM +0200, Bas Nieuwenhuizen wrote:
> This sets the DC tiling options from the modifier, if modifiers
> are used for the FB. This patch by itself does not expose the
> support yet though.
> 
> There is not much validation yet to limit the scope of this
> patch, but the current validation is at the same level as
> the BO metadata path.
> 
> Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
> ---
>  .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 109 +++++++++++++++++-
>  1 file changed, 103 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 6ef7f2f8acab..ac913b8f10ef 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -3754,6 +3754,93 @@ fill_gfx9_plane_attributes_from_flags(struct amdgpu_device *adev,
>  	return 0;
>  }
>  
> +static bool
> +modifier_has_dcc(uint64_t modifier)
> +{
> +	return IS_AMD_FMT_MOD(modifier) && AMD_FMT_MOD_GET(DCC, modifier);
> +}
> +
> +static unsigned
> +modifier_gfx9_swizzle_mode(uint64_t modifier)
> +{
> +	if (modifier == DRM_FORMAT_MOD_LINEAR)
> +		return 0;
> +
> +	return AMD_FMT_MOD_GET(TILE, modifier);
> +}
> +
> +static void
> +fill_gfx9_tiling_info_from_modifier(const struct amdgpu_device *adev,
> +				  union dc_tiling_info *tiling_info,
> +				  uint64_t modifier)
> +{
> +	unsigned int mod_bank_xor_bits = AMD_FMT_MOD_GET(BANK_XOR_BITS, modifier);
> +	unsigned int mod_pipe_xor_bits = AMD_FMT_MOD_GET(PIPE_XOR_BITS, modifier);
> +	unsigned int pkrs_log2 = AMD_FMT_MOD_GET(PACKERS, modifier);
> +	unsigned int pipes_log2 = min(4u, mod_pipe_xor_bits);
> +
> +	fill_gfx9_tiling_info_from_device(adev, tiling_info);
> +
> +	if (!IS_AMD_FMT_MOD(modifier))
> +		return;
> +
> +	tiling_info->gfx9.num_pipes = 1u << pipes_log2;
> +	tiling_info->gfx9.num_shader_engines = 1u << (mod_pipe_xor_bits - pipes_log2);
> +
> +	if (adev->family >= AMDGPU_FAMILY_NV) {
> +		tiling_info->gfx9.num_pkrs = 1u << pkrs_log2;
> +	} else {
> +		tiling_info->gfx9.num_banks = 1u << mod_bank_xor_bits;
> +
> +		/* for DCC we know it isn't rb aligned, so rb_per_se doesn't matter. */
> +	}
> +}
> +
> +static void
> +block_alignment(unsigned int blocksize_log2, unsigned int *width, unsigned int *height)
> +{
> +	unsigned int height_log2 = blocksize_log2 / 2;
> +	unsigned int width_log2 = blocksize_log2 - height_log2;
> +
> +	*width = 1u << width_log2;
> +	*height = 1u << height_log2;
> +}
> +
> +static int
> +fill_gfx9_plane_attributes_from_modifiers(struct amdgpu_device *adev,
> +				      const struct amdgpu_framebuffer *afb,
> +				      const enum surface_pixel_format format,
> +				      const enum dc_rotation_angle rotation,
> +				      const struct plane_size *plane_size,
> +				      union dc_tiling_info *tiling_info,
> +				      struct dc_plane_dcc_param *dcc,
> +				      struct dc_plane_address *address,
> +				      const bool force_disable_dcc)
> +{
> +	const uint64_t modifier = afb->base.modifier;
> +	int ret;
> +
> +	fill_gfx9_tiling_info_from_modifier(adev, tiling_info, modifier);
> +	tiling_info->gfx9.swizzle = modifier_gfx9_swizzle_mode(modifier);
> +
> +	if (modifier_has_dcc(modifier) && !force_disable_dcc) {
> +		uint64_t dcc_address = afb->address + afb->base.offsets[1];
> +
> +		dcc->enable = 1;
> +		dcc->meta_pitch = afb->base.pitches[1];
> +		dcc->independent_64b_blks = AMD_FMT_MOD_GET(DCC_INDEPENDENT_64B, modifier);
> +
> +		address->grph.meta_addr.low_part = lower_32_bits(dcc_address);
> +		address->grph.meta_addr.high_part = upper_32_bits(dcc_address);
> +	}
> +
> +	ret = validate_dcc(adev, format, rotation, tiling_info, dcc, address, plane_size);
> +	if (ret)
> +		return ret;
> +
> +	return 0;
> +}
> +
>  static int
>  fill_plane_buffer_attributes(struct amdgpu_device *adev,
>  			     const struct amdgpu_framebuffer *afb,
> @@ -3823,12 +3910,22 @@ fill_plane_buffer_attributes(struct amdgpu_device *adev,
>  
>  
>  	if (adev->family >= AMDGPU_FAMILY_AI) {
> -		ret = fill_gfx9_plane_attributes_from_flags(adev, afb, format, rotation,
> -							    plane_size, tiling_info, dcc,
> -							    address, tiling_flags,
> -							    force_disable_dcc);
> -		if (ret)
> -			return ret;
> +		if (afb->base.flags & DRM_MODE_FB_MODIFIERS) {
> +			ret = fill_gfx9_plane_attributes_from_modifiers(adev, afb, format,
> +								      rotation, plane_size,
> +								      tiling_info, dcc,
> +								      address,
> +								      force_disable_dcc);
> +			if (ret)
> +				return ret;
> +		} else {
> +			ret = fill_gfx9_plane_attributes_from_flags(adev, afb, format, rotation,
> +								  plane_size, tiling_info, dcc,
> +								  address, tiling_flags,
> +								  force_disable_dcc);
> +			if (ret)
> +				return ret;

So what we've done in i915, but might be too cumbersome with the amdgpu
modifiers, is to map legacy tiling information into modifiers once, at the
beginning of addfb. So in amdgpu_display_user_framebuffer_create(). And
once modifiers are filled in, you ofc set the DRM_MODE_FB_MODIFIERS flag
too in the fb.

Then all the display code only works with modifiers, instead of having a
mix and possible confusion, with breakage when people only test the legacy
path. Which I kinda expect to happen, since amd probably runs with their
own ddx in their CI rig only.

This also avoids a bunch of layering and locking unprettiness, since
display code doesn't need to dig around in gem_bo side of things. On that,
there's another amdgpu_bo_get_tiling_flags in amdgpu_dm_commit_planes
which probably shouldn't be there, and should use computed stuff from
plane state or fb (I changed it to a lockless version to just hack around
locking issues, but still there).

This hopefully/eventually should allow us to entirely phase out the legacy
magic tiling blob attached to bo (we've pulled the trigger on that for
intel now, would have needed to extend the uapi to keep it working was a
good excuse).

Cheers, Daniel

> +		}
>  	} else {
>  		fill_gfx8_tiling_info_from_flags(tiling_info, tiling_flags);
>  	}
> -- 
> 2.28.0
>
Daniel Vetter Aug. 10, 2020, 12:28 p.m. UTC | #2
On Wed, Aug 05, 2020 at 09:32:10AM +0200, daniel@ffwll.ch wrote:
> On Tue, Aug 04, 2020 at 11:31:17PM +0200, Bas Nieuwenhuizen wrote:
> > This sets the DC tiling options from the modifier, if modifiers
> > are used for the FB. This patch by itself does not expose the
> > support yet though.
> > 
> > There is not much validation yet to limit the scope of this
> > patch, but the current validation is at the same level as
> > the BO metadata path.
> > 
> > Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
> > ---
> >  .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 109 +++++++++++++++++-
> >  1 file changed, 103 insertions(+), 6 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > index 6ef7f2f8acab..ac913b8f10ef 100644
> > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > @@ -3754,6 +3754,93 @@ fill_gfx9_plane_attributes_from_flags(struct amdgpu_device *adev,
> >  	return 0;
> >  }
> >  
> > +static bool
> > +modifier_has_dcc(uint64_t modifier)
> > +{
> > +	return IS_AMD_FMT_MOD(modifier) && AMD_FMT_MOD_GET(DCC, modifier);
> > +}
> > +
> > +static unsigned
> > +modifier_gfx9_swizzle_mode(uint64_t modifier)
> > +{
> > +	if (modifier == DRM_FORMAT_MOD_LINEAR)
> > +		return 0;
> > +
> > +	return AMD_FMT_MOD_GET(TILE, modifier);
> > +}
> > +
> > +static void
> > +fill_gfx9_tiling_info_from_modifier(const struct amdgpu_device *adev,
> > +				  union dc_tiling_info *tiling_info,
> > +				  uint64_t modifier)
> > +{
> > +	unsigned int mod_bank_xor_bits = AMD_FMT_MOD_GET(BANK_XOR_BITS, modifier);
> > +	unsigned int mod_pipe_xor_bits = AMD_FMT_MOD_GET(PIPE_XOR_BITS, modifier);
> > +	unsigned int pkrs_log2 = AMD_FMT_MOD_GET(PACKERS, modifier);
> > +	unsigned int pipes_log2 = min(4u, mod_pipe_xor_bits);
> > +
> > +	fill_gfx9_tiling_info_from_device(adev, tiling_info);
> > +
> > +	if (!IS_AMD_FMT_MOD(modifier))
> > +		return;
> > +
> > +	tiling_info->gfx9.num_pipes = 1u << pipes_log2;
> > +	tiling_info->gfx9.num_shader_engines = 1u << (mod_pipe_xor_bits - pipes_log2);
> > +
> > +	if (adev->family >= AMDGPU_FAMILY_NV) {
> > +		tiling_info->gfx9.num_pkrs = 1u << pkrs_log2;
> > +	} else {
> > +		tiling_info->gfx9.num_banks = 1u << mod_bank_xor_bits;
> > +
> > +		/* for DCC we know it isn't rb aligned, so rb_per_se doesn't matter. */
> > +	}
> > +}
> > +
> > +static void
> > +block_alignment(unsigned int blocksize_log2, unsigned int *width, unsigned int *height)
> > +{
> > +	unsigned int height_log2 = blocksize_log2 / 2;
> > +	unsigned int width_log2 = blocksize_log2 - height_log2;
> > +
> > +	*width = 1u << width_log2;
> > +	*height = 1u << height_log2;
> > +}
> > +
> > +static int
> > +fill_gfx9_plane_attributes_from_modifiers(struct amdgpu_device *adev,
> > +				      const struct amdgpu_framebuffer *afb,
> > +				      const enum surface_pixel_format format,
> > +				      const enum dc_rotation_angle rotation,
> > +				      const struct plane_size *plane_size,
> > +				      union dc_tiling_info *tiling_info,
> > +				      struct dc_plane_dcc_param *dcc,
> > +				      struct dc_plane_address *address,
> > +				      const bool force_disable_dcc)
> > +{
> > +	const uint64_t modifier = afb->base.modifier;
> > +	int ret;
> > +
> > +	fill_gfx9_tiling_info_from_modifier(adev, tiling_info, modifier);
> > +	tiling_info->gfx9.swizzle = modifier_gfx9_swizzle_mode(modifier);
> > +
> > +	if (modifier_has_dcc(modifier) && !force_disable_dcc) {
> > +		uint64_t dcc_address = afb->address + afb->base.offsets[1];
> > +
> > +		dcc->enable = 1;
> > +		dcc->meta_pitch = afb->base.pitches[1];
> > +		dcc->independent_64b_blks = AMD_FMT_MOD_GET(DCC_INDEPENDENT_64B, modifier);
> > +
> > +		address->grph.meta_addr.low_part = lower_32_bits(dcc_address);
> > +		address->grph.meta_addr.high_part = upper_32_bits(dcc_address);
> > +	}
> > +
> > +	ret = validate_dcc(adev, format, rotation, tiling_info, dcc, address, plane_size);
> > +	if (ret)
> > +		return ret;
> > +
> > +	return 0;
> > +}
> > +
> >  static int
> >  fill_plane_buffer_attributes(struct amdgpu_device *adev,
> >  			     const struct amdgpu_framebuffer *afb,
> > @@ -3823,12 +3910,22 @@ fill_plane_buffer_attributes(struct amdgpu_device *adev,
> >  
> >  
> >  	if (adev->family >= AMDGPU_FAMILY_AI) {
> > -		ret = fill_gfx9_plane_attributes_from_flags(adev, afb, format, rotation,
> > -							    plane_size, tiling_info, dcc,
> > -							    address, tiling_flags,
> > -							    force_disable_dcc);
> > -		if (ret)
> > -			return ret;
> > +		if (afb->base.flags & DRM_MODE_FB_MODIFIERS) {
> > +			ret = fill_gfx9_plane_attributes_from_modifiers(adev, afb, format,
> > +								      rotation, plane_size,
> > +								      tiling_info, dcc,
> > +								      address,
> > +								      force_disable_dcc);
> > +			if (ret)
> > +				return ret;
> > +		} else {
> > +			ret = fill_gfx9_plane_attributes_from_flags(adev, afb, format, rotation,
> > +								  plane_size, tiling_info, dcc,
> > +								  address, tiling_flags,
> > +								  force_disable_dcc);
> > +			if (ret)
> > +				return ret;
> 
> So what we've done in i915, but might be too cumbersome with the amdgpu
> modifiers, is to map legacy tiling information into modifiers once, at the
> beginning of addfb. So in amdgpu_display_user_framebuffer_create(). And
> once modifiers are filled in, you ofc set the DRM_MODE_FB_MODIFIERS flag
> too in the fb.
> 
> Then all the display code only works with modifiers, instead of having a
> mix and possible confusion, with breakage when people only test the legacy
> path. Which I kinda expect to happen, since amd probably runs with their
> own ddx in their CI rig only.
> 
> This also avoids a bunch of layering and locking unprettiness, since
> display code doesn't need to dig around in gem_bo side of things. On that,
> there's another amdgpu_bo_get_tiling_flags in amdgpu_dm_commit_planes
> which probably shouldn't be there, and should use computed stuff from
> plane state or fb (I changed it to a lockless version to just hack around
> locking issues, but still there).
> 
> This hopefully/eventually should allow us to entirely phase out the legacy
> magic tiling blob attached to bo (we've pulled the trigger on that for
> intel now, would have needed to extend the uapi to keep it working was a
> good excuse).

Ok just learned that amdgpu hat set/get_tiling, so I'm upgrading my idea
here to a very strong recommendation, i.e. please do this except if
there's and amd ddx which somehow wants to change tiling mode while a fb
exists, and expects this to propagate.

In i915 we even disallow the set_tiling ioctl with an error if an fb
exists, just to make sure userspace behaves. Even if userspace uses
set_tiling, this way we can at least enforce the same semantics of "client
can't pull compositor over the table with a set_tiling at the wrong time"
of modifiers.
-Daniel

> 
> Cheers, Daniel
> 
> > +		}
> >  	} else {
> >  		fill_gfx8_tiling_info_from_flags(tiling_info, tiling_flags);
> >  	}
> > -- 
> > 2.28.0
> > 
> 
> -- 
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
Michel Dänzer Aug. 10, 2020, 12:49 p.m. UTC | #3
On 2020-08-10 2:28 p.m., Daniel Vetter wrote:
>
> Ok just learned that amdgpu hat set/get_tiling, so I'm upgrading my idea
> here to a very strong recommendation, i.e. please do this except if
> there's and amd ddx which somehow wants to change tiling mode while a fb
> exists, and expects this to propagate.
> 
> In i915 we even disallow the set_tiling ioctl with an error if an fb
> exists, just to make sure userspace behaves. Even if userspace uses
> set_tiling, this way we can at least enforce the same semantics of "client
> can't pull compositor over the table with a set_tiling at the wrong time"
> of modifiers.

FWIW, xf86-video-amdgpu doesn't have any code to set the tiling
metadata, only Mesa and presumably AMD's Vulkan/OpenGL UMDs do.
Daniel Vetter Aug. 10, 2020, 1:09 p.m. UTC | #4
On Mon, Aug 10, 2020 at 02:49:00PM +0200, Michel Dänzer wrote:
> On 2020-08-10 2:28 p.m., Daniel Vetter wrote:
> >
> > Ok just learned that amdgpu hat set/get_tiling, so I'm upgrading my idea
> > here to a very strong recommendation, i.e. please do this except if
> > there's and amd ddx which somehow wants to change tiling mode while a fb
> > exists, and expects this to propagate.
> > 
> > In i915 we even disallow the set_tiling ioctl with an error if an fb
> > exists, just to make sure userspace behaves. Even if userspace uses
> > set_tiling, this way we can at least enforce the same semantics of "client
> > can't pull compositor over the table with a set_tiling at the wrong time"
> > of modifiers.
> 
> FWIW, xf86-video-amdgpu doesn't have any code to set the tiling
> metadata, only Mesa and presumably AMD's Vulkan/OpenGL UMDs do.

Ah right you do everything with glamour, so this should never show up as a
problem.
-Daniel
Bas Nieuwenhuizen Aug. 10, 2020, 2:13 p.m. UTC | #5
On Mon, Aug 10, 2020 at 3:09 PM Daniel Vetter <daniel@ffwll.ch> wrote:
>
> On Mon, Aug 10, 2020 at 02:49:00PM +0200, Michel Dänzer wrote:
> > On 2020-08-10 2:28 p.m., Daniel Vetter wrote:
> > >
> > > Ok just learned that amdgpu hat set/get_tiling, so I'm upgrading my idea
> > > here to a very strong recommendation, i.e. please do this except if
> > > there's and amd ddx which somehow wants to change tiling mode while a fb
> > > exists, and expects this to propagate.
> > >
> > > In i915 we even disallow the set_tiling ioctl with an error if an fb
> > > exists, just to make sure userspace behaves. Even if userspace uses
> > > set_tiling, this way we can at least enforce the same semantics of "client
> > > can't pull compositor over the table with a set_tiling at the wrong time"
> > > of modifiers.
> >
> > FWIW, xf86-video-amdgpu doesn't have any code to set the tiling
> > metadata, only Mesa and presumably AMD's Vulkan/OpenGL UMDs do.
>
> Ah right you do everything with glamour, so this should never show up as a
> problem.

I think it is a good idea to do so, but cannot do it completely in
this series as we don't define modifiers for GFX6-GFX8 GPU generations
yet. (wanted to leave these out for a bit to reduce the scope for the
initial version)

That said, there is a series that captures the tiling flags on FB
creation: https://patchwork.freedesktop.org/series/80109/

> -Daniel
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Daniel Vetter Aug. 10, 2020, 2:20 p.m. UTC | #6
On Mon, Aug 10, 2020 at 4:13 PM Bas Nieuwenhuizen
<bas@basnieuwenhuizen.nl> wrote:
>
> On Mon, Aug 10, 2020 at 3:09 PM Daniel Vetter <daniel@ffwll.ch> wrote:
> >
> > On Mon, Aug 10, 2020 at 02:49:00PM +0200, Michel Dänzer wrote:
> > > On 2020-08-10 2:28 p.m., Daniel Vetter wrote:
> > > >
> > > > Ok just learned that amdgpu hat set/get_tiling, so I'm upgrading my idea
> > > > here to a very strong recommendation, i.e. please do this except if
> > > > there's and amd ddx which somehow wants to change tiling mode while a fb
> > > > exists, and expects this to propagate.
> > > >
> > > > In i915 we even disallow the set_tiling ioctl with an error if an fb
> > > > exists, just to make sure userspace behaves. Even if userspace uses
> > > > set_tiling, this way we can at least enforce the same semantics of "client
> > > > can't pull compositor over the table with a set_tiling at the wrong time"
> > > > of modifiers.
> > >
> > > FWIW, xf86-video-amdgpu doesn't have any code to set the tiling
> > > metadata, only Mesa and presumably AMD's Vulkan/OpenGL UMDs do.
> >
> > Ah right you do everything with glamour, so this should never show up as a
> > problem.
>
> I think it is a good idea to do so, but cannot do it completely in
> this series as we don't define modifiers for GFX6-GFX8 GPU generations
> yet. (wanted to leave these out for a bit to reduce the scope for the
> initial version)

Hm right, that makes it a bit awkward.

> That said, there is a series that captures the tiling flags on FB
> creation: https://patchwork.freedesktop.org/series/80109/

Yeah, but it only pushes it down into the state objects. Good first
step, what I'm proposing is to push it all the way into addfb/struct
drm_framebuffer. Since drm_framebuffer is also an invariant thing it
makes the most sense to keep that there. I'm also discussing with
Nicholas about what would be the ideal end state.

But yeah maybe one thing at time.
-Daniel

>
> > -Daniel
> > --
> > Daniel Vetter
> > Software Engineer, Intel Corporation
> > http://blog.ffwll.ch
> > _______________________________________________
> > amd-gfx mailing list
> > amd-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Patch
diff mbox series

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 6ef7f2f8acab..ac913b8f10ef 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -3754,6 +3754,93 @@  fill_gfx9_plane_attributes_from_flags(struct amdgpu_device *adev,
 	return 0;
 }
 
+static bool
+modifier_has_dcc(uint64_t modifier)
+{
+	return IS_AMD_FMT_MOD(modifier) && AMD_FMT_MOD_GET(DCC, modifier);
+}
+
+static unsigned
+modifier_gfx9_swizzle_mode(uint64_t modifier)
+{
+	if (modifier == DRM_FORMAT_MOD_LINEAR)
+		return 0;
+
+	return AMD_FMT_MOD_GET(TILE, modifier);
+}
+
+static void
+fill_gfx9_tiling_info_from_modifier(const struct amdgpu_device *adev,
+				  union dc_tiling_info *tiling_info,
+				  uint64_t modifier)
+{
+	unsigned int mod_bank_xor_bits = AMD_FMT_MOD_GET(BANK_XOR_BITS, modifier);
+	unsigned int mod_pipe_xor_bits = AMD_FMT_MOD_GET(PIPE_XOR_BITS, modifier);
+	unsigned int pkrs_log2 = AMD_FMT_MOD_GET(PACKERS, modifier);
+	unsigned int pipes_log2 = min(4u, mod_pipe_xor_bits);
+
+	fill_gfx9_tiling_info_from_device(adev, tiling_info);
+
+	if (!IS_AMD_FMT_MOD(modifier))
+		return;
+
+	tiling_info->gfx9.num_pipes = 1u << pipes_log2;
+	tiling_info->gfx9.num_shader_engines = 1u << (mod_pipe_xor_bits - pipes_log2);
+
+	if (adev->family >= AMDGPU_FAMILY_NV) {
+		tiling_info->gfx9.num_pkrs = 1u << pkrs_log2;
+	} else {
+		tiling_info->gfx9.num_banks = 1u << mod_bank_xor_bits;
+
+		/* for DCC we know it isn't rb aligned, so rb_per_se doesn't matter. */
+	}
+}
+
+static void
+block_alignment(unsigned int blocksize_log2, unsigned int *width, unsigned int *height)
+{
+	unsigned int height_log2 = blocksize_log2 / 2;
+	unsigned int width_log2 = blocksize_log2 - height_log2;
+
+	*width = 1u << width_log2;
+	*height = 1u << height_log2;
+}
+
+static int
+fill_gfx9_plane_attributes_from_modifiers(struct amdgpu_device *adev,
+				      const struct amdgpu_framebuffer *afb,
+				      const enum surface_pixel_format format,
+				      const enum dc_rotation_angle rotation,
+				      const struct plane_size *plane_size,
+				      union dc_tiling_info *tiling_info,
+				      struct dc_plane_dcc_param *dcc,
+				      struct dc_plane_address *address,
+				      const bool force_disable_dcc)
+{
+	const uint64_t modifier = afb->base.modifier;
+	int ret;
+
+	fill_gfx9_tiling_info_from_modifier(adev, tiling_info, modifier);
+	tiling_info->gfx9.swizzle = modifier_gfx9_swizzle_mode(modifier);
+
+	if (modifier_has_dcc(modifier) && !force_disable_dcc) {
+		uint64_t dcc_address = afb->address + afb->base.offsets[1];
+
+		dcc->enable = 1;
+		dcc->meta_pitch = afb->base.pitches[1];
+		dcc->independent_64b_blks = AMD_FMT_MOD_GET(DCC_INDEPENDENT_64B, modifier);
+
+		address->grph.meta_addr.low_part = lower_32_bits(dcc_address);
+		address->grph.meta_addr.high_part = upper_32_bits(dcc_address);
+	}
+
+	ret = validate_dcc(adev, format, rotation, tiling_info, dcc, address, plane_size);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
 static int
 fill_plane_buffer_attributes(struct amdgpu_device *adev,
 			     const struct amdgpu_framebuffer *afb,
@@ -3823,12 +3910,22 @@  fill_plane_buffer_attributes(struct amdgpu_device *adev,
 
 
 	if (adev->family >= AMDGPU_FAMILY_AI) {
-		ret = fill_gfx9_plane_attributes_from_flags(adev, afb, format, rotation,
-							    plane_size, tiling_info, dcc,
-							    address, tiling_flags,
-							    force_disable_dcc);
-		if (ret)
-			return ret;
+		if (afb->base.flags & DRM_MODE_FB_MODIFIERS) {
+			ret = fill_gfx9_plane_attributes_from_modifiers(adev, afb, format,
+								      rotation, plane_size,
+								      tiling_info, dcc,
+								      address,
+								      force_disable_dcc);
+			if (ret)
+				return ret;
+		} else {
+			ret = fill_gfx9_plane_attributes_from_flags(adev, afb, format, rotation,
+								  plane_size, tiling_info, dcc,
+								  address, tiling_flags,
+								  force_disable_dcc);
+			if (ret)
+				return ret;
+		}
 	} else {
 		fill_gfx8_tiling_info_from_flags(tiling_info, tiling_flags);
 	}