[53/56] KVM: arm64: Rename kvm_vcpu_dabt_isextabt()

Message ID	20200805175700.62775-54-maz@kernel.org (mailing list archive)
State	New, archived
Headers	show Return-Path: <SRS0=UpKl=BP=vger.kernel.org=kvm-owner@kernel.org> From: Marc Zyngier <maz@kernel.org> To: Paolo Bonzini <pbonzini@redhat.com> Cc: Alexander Graf <graf@amazon.com>, Alexandru Elisei <alexandru.elisei@arm.com>, Andrew Scull <ascull@google.com>, Catalin Marinas <catalin.marinas@arm.com>, Christoffer Dall <christoffer.dall@arm.com>, David Brazdil <dbrazdil@google.com>, Eric Auger <eric.auger@redhat.com>, Gavin Shan <gshan@redhat.com>, James Morse <james.morse@arm.com>, Mark Rutland <mark.rutland@arm.com>, Peng Hao <richard.peng@oppo.com>, Quentin Perret <qperret@google.com>, Will Deacon <will@kernel.org>, Julien Thierry <julien.thierry.kdev@gmail.com>, Suzuki K Poulose <suzuki.poulose@arm.com>, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, kernel-team@android.com Subject: [PATCH 53/56] KVM: arm64: Rename kvm_vcpu_dabt_isextabt() Date: Wed, 5 Aug 2020 18:56:57 +0100 Message-Id: <20200805175700.62775-54-maz@kernel.org> In-Reply-To: <20200805175700.62775-1-maz@kernel.org> References: <20200805175700.62775-1-maz@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: kvm-owner@vger.kernel.org Precedence: bulk
Series	[01/56] KVM: arm64: Enable Address Authentication at EL2 if available \| expand [01/56] KVM: arm64: Enable Address Authentication at EL2 if available [02/56] KVM: arm64: Allow ARM64_PTR_AUTH when ARM64_VHE=n [03/56] KVM: arm64: Allow PtrAuth to be enabled from userspace on non-VHE systems [04/56] KVM: arm64: Check HCR_EL2 instead of shadow copy to swap PtrAuth registers [05/56] KVM: arm64: Simplify PtrAuth alternative patching [06/56] KVM: arm64: Allow in-atomic injection of SPIs [07/56] arm64: kvm: Remove kern_hyp_va from get_vcpu_ptr [08/56] KVM: arm64: Drop the target_table[] indirection [09/56] KVM: arm64: Tolerate an empty target_table list [10/56] KVM: arm64: Move ACTLR_EL1 emulation to the sys_reg_descs array [11/56] KVM: arm64: Remove target_table from exit handlers [12/56] KVM: arm64: Remove the target table [13/56] KVM: arm64: Fix symbol dependency in __hyp_call_panic_nvhe [14/56] KVM: arm64: Move __smccc_workaround_1_smc to .rodata [15/56] KVM: arm64: Add build rules for separate VHE/nVHE object files [16/56] KVM: arm64: Use build-time defines in has_vhe() [17/56] KVM: arm64: Handle calls to prefixed hyp functions [18/56] KVM: arm64: Build hyp-entry.S separately for VHE/nVHE [19/56] KVM: arm64: Move hyp-init.S to nVHE [20/56] KVM: arm64: Duplicate hyp/tlb.c for VHE/nVHE [21/56] KVM: arm64: Split hyp/switch.c to VHE/nVHE [22/56] KVM: arm64: Split hyp/debug-sr.c to VHE/nVHE [23/56] KVM: arm64: Split hyp/sysreg-sr.c to VHE/nVHE [24/56] KVM: arm64: Duplicate hyp/timer-sr.c for VHE/nVHE [25/56] KVM: arm64: Compile remaining hyp/ files for both VHE/nVHE [26/56] KVM: arm64: Remove __hyp_text macro, use build rules instead [27/56] KVM: arm64: Lift instrumentation restrictions on VHE [28/56] KVM: arm64: vgic-its: Change default outer cacheability for {PEND, PROP}BASER [29/56] KVM: arm64: Drop long gone function parameter documentation [30/56] KVM: arm64: Rename HSR to ESR [31/56] arm64: Detect the ARMv8.4 TTL feature [32/56] arm64: Document SW reserved PTE/PMD bits in Stage-2 descriptors [33/56] arm64: Add level-hinted TLB invalidation helper [34/56] KVM: arm64: Factor out stage 2 page table data from struct kvm [35/56] KVM: arm64: Use TTL hint in when invalidating stage-2 translations [36/56] KVM: arm64: Introduce accessor for ctxt->sys_reg [37/56] KVM: arm64: hyp: Use ctxt_sys_reg/__vcpu_sys_reg instead of raw sys_regs access [38/56] KVM: arm64: sve: Use __vcpu_sys_reg() instead of raw sys_regs access [39/56] KVM: arm64: pauth: Use ctxt_sys_reg() instead of raw sys_regs access [40/56] KVM: arm64: debug: Drop useless vpcu parameter [41/56] KVM: arm64: Make struct kvm_regs userspace-only [42/56] KVM: arm64: Move ELR_EL1 to the system register array [43/56] KVM: arm64: Move SP_EL1 to the system register array [44/56] KVM: arm64: Disintegrate SPSR array [45/56] KVM: arm64: Move SPSR_EL1 to the system register array [46/56] KVM: arm64: timers: Rename kvm_timer_sync_hwstate to kvm_timer_sync_user [47/56] KVM: arm64: timers: Move timer registers to the sys_regs file [48/56] KVM: arm64: Don't use has_vhe() for CHOOSE_HYP_SYM() [49/56] KVM: arm64: Make nVHE ASLR conditional on RANDOMIZE_BASE [50/56] KVM: arm64: Substitute RANDOMIZE_BASE for HARDEN_EL2_VECTORS [51/56] KVM: arm64: Ensure that all nVHE hyp code is in .hyp.text [52/56] KVM: arm: Add trace name for ARM_NISV [53/56] KVM: arm64: Rename kvm_vcpu_dabt_isextabt() [54/56] KVM: arm64: Handle data and instruction external aborts the same way [55/56] KVM: arm64: Don't skip cache maintenance for read-only memslots [56/56] KVM: arm64: Move S1PTW S2 fault logic out of io_mem_abort()

Message ID

20200805175700.62775-54-maz@kernel.org (mailing list archive)

State

New, archived

Headers

From: Marc Zyngier <maz@kernel.org>
To: Paolo Bonzini <pbonzini@redhat.com>
Cc: Alexander Graf <graf@amazon.com>,
        Alexandru Elisei <alexandru.elisei@arm.com>,
        Andrew Scull <ascull@google.com>,
        Catalin Marinas <catalin.marinas@arm.com>,
        Christoffer Dall <christoffer.dall@arm.com>,
        David Brazdil <dbrazdil@google.com>,
        Eric Auger <eric.auger@redhat.com>,
        Gavin Shan <gshan@redhat.com>,
        James Morse <james.morse@arm.com>,
        Mark Rutland <mark.rutland@arm.com>,
        Peng Hao <richard.peng@oppo.com>,
        Quentin Perret <qperret@google.com>,
        Will Deacon <will@kernel.org>,
        Julien Thierry <julien.thierry.kdev@gmail.com>,
        Suzuki K Poulose <suzuki.poulose@arm.com>,
        linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu,
        kvm@vger.kernel.org, kernel-team@android.com
Subject: [PATCH 53/56] KVM: arm64: Rename kvm_vcpu_dabt_isextabt()
Date: Wed,  5 Aug 2020 18:56:57 +0100
Message-Id: <20200805175700.62775-54-maz@kernel.org>
In-Reply-To: <20200805175700.62775-1-maz@kernel.org>
References: <20200805175700.62775-1-maz@kernel.org>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
Sender: kvm-owner@vger.kernel.org
Precedence: bulk

Series

[01/56] KVM: arm64: Enable Address Authentication at EL2 if available | expand

Commit Message

Marc Zyngier Aug. 5, 2020, 5:56 p.m. UTC

From: Will Deacon <will@kernel.org>

kvm_vcpu_dabt_isextabt() is not specific to data aborts and, unlike
kvm_vcpu_dabt_issext(), has nothing to do with sign extension.

Rename it to 'kvm_vcpu_abt_issea()'.

Signed-off-by: Will Deacon <will@kernel.org>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Quentin Perret <qperret@google.com>
Link: https://lore.kernel.org/r/20200729102821.23392-2-will@kernel.org
---
 arch/arm64/include/asm/kvm_emulate.h | 2 +-
 arch/arm64/kvm/hyp/switch.c          | 2 +-
 arch/arm64/kvm/mmu.c                 | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/include/asm/kvm_emulate.h b/arch/arm64/include/asm/kvm_emulate.h
index c9ba0df47f7d..e0536946abed 100644
--- a/arch/arm64/include/asm/kvm_emulate.h
+++ b/arch/arm64/include/asm/kvm_emulate.h
@@ -366,7 +366,7 @@  static __always_inline u8 kvm_vcpu_trap_get_fault_type(const struct kvm_vcpu *vc
 	return kvm_vcpu_get_esr(vcpu) & ESR_ELx_FSC_TYPE;
 }
 
-static __always_inline bool kvm_vcpu_dabt_isextabt(const struct kvm_vcpu *vcpu)
+static __always_inline bool kvm_vcpu_abt_issea(const struct kvm_vcpu *vcpu)
 {
 	switch (kvm_vcpu_trap_get_fault(vcpu)) {
 	case FSC_SEA:
diff --git a/arch/arm64/kvm/hyp/switch.c b/arch/arm64/kvm/hyp/switch.c
index 5164074c1ae1..36a1f0a9ce2e 100644
--- a/arch/arm64/kvm/hyp/switch.c
+++ b/arch/arm64/kvm/hyp/switch.c
@@ -594,7 +594,7 @@  static bool __hyp_text fixup_guest_exit(struct kvm_vcpu *vcpu, u64 *exit_code)
 		valid = kvm_vcpu_trap_get_class(vcpu) == ESR_ELx_EC_DABT_LOW &&
 			kvm_vcpu_trap_get_fault_type(vcpu) == FSC_FAULT &&
 			kvm_vcpu_dabt_isvalid(vcpu) &&
-			!kvm_vcpu_dabt_isextabt(vcpu) &&
+			!kvm_vcpu_abt_issea(vcpu) &&
 			!kvm_vcpu_dabt_iss1tw(vcpu);
 
 		if (valid) {
diff --git a/arch/arm64/kvm/mmu.c b/arch/arm64/kvm/mmu.c
index 36506112480e..8004f1f68946 100644
--- a/arch/arm64/kvm/mmu.c
+++ b/arch/arm64/kvm/mmu.c
@@ -2074,7 +2074,7 @@  int kvm_handle_guest_abort(struct kvm_vcpu *vcpu, struct kvm_run *run)
 	is_iabt = kvm_vcpu_trap_is_iabt(vcpu);
 
 	/* Synchronous External Abort? */
-	if (kvm_vcpu_dabt_isextabt(vcpu)) {
+	if (kvm_vcpu_abt_issea(vcpu)) {
 		/*
 		 * For RAS the host kernel may handle this abort.
 		 * There is no need to pass the error into the guest.

[53/56] KVM: arm64: Rename kvm_vcpu_dabt_isextabt()

Commit Message

Patch