From patchwork Thu Aug 6 12:18:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hector Yuan X-Patchwork-Id: 11703787 X-Patchwork-Delegate: viresh.linux@gmail.com Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1D2F0722 for ; Thu, 6 Aug 2020 17:54:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 809BA206C3 for ; Thu, 6 Aug 2020 17:54:20 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="Y2xVrIuw" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726789AbgHFRx4 (ORCPT ); Thu, 6 Aug 2020 13:53:56 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:57026 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1728158AbgHFQaz (ORCPT ); Thu, 6 Aug 2020 12:30:55 -0400 X-UUID: 8a705a9515e04b39a6104849cbefd20c-20200806 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=hq0WCel81lE8aBCRSm65DN3f8dXfFefcGZQW+R17dLo=; b=Y2xVrIuwGI/P8R/00nM96g+DhrSFCLQRUZXV4uPxR4pI6N6PwHAWxxJlXn+q+xOUH8VkQIA/emt/xfOhOQcwlPclkctFwcm2+47lmBDJjhhjcoJRHh5lxD9SO4tE6uDtl5BB06K7VZ0GNJz+jkCAMxMZWXGB2MyIF8eyIePyNIA=; X-UUID: 8a705a9515e04b39a6104849cbefd20c-20200806 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 63181443; Thu, 06 Aug 2020 20:18:46 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 6 Aug 2020 20:18:43 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 6 Aug 2020 20:18:44 +0800 From: Hector Yuan To: , , , , "Rafael J. Wysocki" , Viresh Kumar , Rob Herring , Catalin Marinas , Will Deacon , Matthias Brugger , Bjorn Andersson , Shawn Guo , Li Yang , Vinod Koul , Arnd Bergmann , Anson Huang , Geert Uytterhoeven , Olof Johansson CC: , Subject: [PATCH v1 2/2] dt-bindings: cpufreq: add MediaTek cpufreq bindings Date: Thu, 6 Aug 2020 20:18:40 +0800 Message-ID: <1596716320-19811-3-git-send-email-hector.yuan@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1596716320-19811-1-git-send-email-hector.yuan@mediatek.com> References: <1596716320-19811-1-git-send-email-hector.yuan@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: "Hector.Yuan" Add devicetree bindings for MediaTek HW driver. Signed-off-by: Hector.Yuan --- .../bindings/cpufreq/cpufreq-mediatek-hw.yaml | 56 ++++++++++++++++++++ 1 file changed, 56 insertions(+) create mode 100644 Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml new file mode 100644 index 0000000..2a35098 --- /dev/null +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/cpufreq/cpufreq-mediatek-hw.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek's CPUFREQ Bindings + +maintainers: + - Hector Yuan + +description: + CPUFREQ HW is a hardware engine used by MediaTek + SoCs to manage frequency in hardware. It is capable of controlling frequency + for multiple clusters. + +properties: + compatible: + const: mediatek,cpufreq-hw + + reg: + minItems: 1 + maxItems: 2 + description: | + Addresses and sizes for the memory of the HW bases in each frequency domain. + + reg-names: + items: + - const: "freq-domain0" + - const: "freq-domain1" + description: | + Frequency domain name. + + "#freq-domain-cells": + const: 1 + description: | + Number of cells in a freqency domain specifier. + +required: + - compatible + - reg + - reg-names + - "#freq-domain-cells" + +additionalProperties: false + +examples: + - | + cpufreq_hw: cpufreq@11bc00 { + compatible = "mediatek,cpufreq-hw"; + reg = <0 0x11bc10 0 0x8c>, + <0 0x11bca0 0 0x8c>; + reg-names = "freq-domain0", "freq-domain1"; + #freq-domain-cells = <1>; + }; +