From patchwork Wed Aug 12 09:46:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sit, Michael Wei Hong" X-Patchwork-Id: 11710597 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id F35C014E3 for ; Wed, 12 Aug 2020 09:54:23 +0000 (UTC) Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 85A5A20838 for ; Wed, 12 Aug 2020 09:54:23 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=alsa-project.org header.i=@alsa-project.org header.b="iueSxsTn" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 85A5A20838 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=alsa-devel-bounces@alsa-project.org Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id 750361677; Wed, 12 Aug 2020 11:53:33 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz 750361677 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1597226061; bh=XSZGlvc++BiHwcON+tn3k9hBdCPO6vrV2Z7lx3Y6Yyk=; h=From:To:Subject:Date:In-Reply-To:References:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=iueSxsTnjTLI8M++gXFkmd4qCCCyOk/N+cjIxsdvSWy0x6hFspL/KOj3XJDJ3IFeM xGBzegSqN0tl6qnFuOC/UBsUB7V6wD/E7Zpy5JIhn+gJ63AJOafMQwx/bwCKoUhWjs zlCRm6TY07xA1CA30cvgYQB9lSzvjdd3B62ztTg8= Received: from alsa1.perex.cz (localhost.localdomain [127.0.0.1]) by alsa1.perex.cz (Postfix) with ESMTP id 3E2E1F8027B; Wed, 12 Aug 2020 11:52:41 +0200 (CEST) X-Original-To: alsa-devel@alsa-project.org Delivered-To: alsa-devel@alsa-project.org Received: by alsa1.perex.cz (Postfix, from userid 50401) id AE3CBF802C2; Wed, 12 Aug 2020 11:52:38 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on alsa1.perex.cz X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id 26804F80245 for ; Wed, 12 Aug 2020 11:52:31 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz 26804F80245 IronPort-SDR: w0XWlmORHEqtV02e4oV4SnELsrh4cbd5kG2UlzkdhsUu3DXtLmazauQg2nPS0WsfpWxrXwB69d llYq+huPkk1w== X-IronPort-AV: E=McAfee;i="6000,8403,9710"; a="215446660" X-IronPort-AV: E=Sophos;i="5.76,303,1592895600"; d="scan'208";a="215446660" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Aug 2020 02:52:26 -0700 IronPort-SDR: JmEjJ0k1aqHJq3USTBn2lc6XecyCxjsVqOKACqTRUNhbXfSUnYXlStrmdP3NZMZOWXRgRsOQAC mGhJZWZMwS3g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.76,303,1592895600"; d="scan'208";a="290983660" Received: from mike-ilbpg1.png.intel.com ([10.88.227.76]) by orsmga003.jf.intel.com with ESMTP; 12 Aug 2020 02:52:23 -0700 From: Michael Sit Wei Hong To: alsa-devel@alsa-project.org Subject: [PATCH v2 3/3] ASoC: codec: tlv3204: Moving GPIO reset and add ADC reset Date: Wed, 12 Aug 2020 17:46:31 +0800 Message-Id: <20200812094631.4698-4-michael.wei.hong.sit@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200812094631.4698-1-michael.wei.hong.sit@intel.com> References: <20200812094631.4698-1-michael.wei.hong.sit@intel.com> Cc: cezary.rojewski@intel.com, a-estrada@ti.com, andriy.shevchenko@intel.com, zakkaye@ti.com, tiwai@suse.com, jee.heng.sia@intel.com, pierre-louis.bossart@linux.intel.com, liam.r.girdwood@linux.intel.com, broonie@kernel.org, dmurphy@ti.com X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" Moving GPIO reset to a later stage and before clock registration to ensure that the host system and codec clocks are in sync. If the host register clock values prior to gpio reset, the last configured codec clock is registered to the host. The codec then gets gpio resetted setting the codec clocks to their default value, causing a mismatch. Host system will skip clock setting thinking the codec clocks are already at the requested rate. ADC reset is added to ensure the next audio capture does not have undesired artifacts. It is probably related to the original code where the probe function resets the ADC prior to 1st record. Signed-off-by: Michael Sit Wei Hong Reviewed-by: Sia Jee Heng Reviewed-by: Pierre-Louis Bossart --- sound/soc/codecs/tlv320aic32x4.c | 47 ++++++++++++++++++++++++-------- 1 file changed, 35 insertions(+), 12 deletions(-) diff --git a/sound/soc/codecs/tlv320aic32x4.c b/sound/soc/codecs/tlv320aic32x4.c index 6c2338ea5d8d..8dcea566b375 100644 --- a/sound/soc/codecs/tlv320aic32x4.c +++ b/sound/soc/codecs/tlv320aic32x4.c @@ -50,6 +50,28 @@ struct aic32x4_priv { struct device *dev; }; +static int aic32x4_reset_adc(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); + u32 adc_reg; + + /* + * Workaround: the datasheet does not mention a required programming + * sequence but experiments show the ADC needs to be reset after each + * capture to avoid audible artifacts. + */ + switch (event) { + case SND_SOC_DAPM_POST_PMD: + adc_reg = snd_soc_component_read(component, AIC32X4_ADCSETUP); + snd_soc_component_write(component, AIC32X4_ADCSETUP, adc_reg | + AIC32X4_LADC_EN | AIC32X4_RADC_EN); + snd_soc_component_write(component, AIC32X4_ADCSETUP, adc_reg); + break; + } + return 0; +}; + static int mic_bias_event(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event) { @@ -434,6 +456,7 @@ static const struct snd_soc_dapm_widget aic32x4_dapm_widgets[] = { SND_SOC_DAPM_SUPPLY("Mic Bias", AIC32X4_MICBIAS, 6, 0, mic_bias_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), + SND_SOC_DAPM_POST("ADC Reset", aic32x4_reset_adc), SND_SOC_DAPM_OUTPUT("HPL"), SND_SOC_DAPM_OUTPUT("HPR"), @@ -665,8 +688,8 @@ static int aic32x4_set_processing_blocks(struct snd_soc_component *component, } static int aic32x4_setup_clocks(struct snd_soc_component *component, - unsigned int sample_rate, unsigned int channel, - unsigned int bit_depth) + unsigned int sample_rate, unsigned int channel, + unsigned int bit_depth) { u8 aosr; u16 dosr; @@ -958,12 +981,6 @@ static int aic32x4_component_probe(struct snd_soc_component *component) if (ret) return ret; - if (gpio_is_valid(aic32x4->rstn_gpio)) { - ndelay(10); - gpio_set_value(aic32x4->rstn_gpio, 1); - mdelay(1); - } - snd_soc_component_write(component, AIC32X4_RESET, 0x01); if (aic32x4->setup) @@ -1196,10 +1213,6 @@ int aic32x4_probe(struct device *dev, struct regmap *regmap) aic32x4->mclk_name = "mclk"; } - ret = aic32x4_register_clocks(dev, aic32x4->mclk_name); - if (ret) - return ret; - if (gpio_is_valid(aic32x4->rstn_gpio)) { ret = devm_gpio_request_one(dev, aic32x4->rstn_gpio, GPIOF_OUT_INIT_LOW, "tlv320aic32x4 rstn"); @@ -1221,6 +1234,16 @@ int aic32x4_probe(struct device *dev, struct regmap *regmap) return ret; } + if (gpio_is_valid(aic32x4->rstn_gpio)) { + ndelay(10); + gpio_set_value_cansleep(aic32x4->rstn_gpio, 1); + mdelay(1); + } + + ret = aic32x4_register_clocks(dev, aic32x4->mclk_name); + if (ret) + return ret; + return 0; } EXPORT_SYMBOL(aic32x4_probe);