diff mbox series

[16/36] arm64: defconfig: Enable R8A774E1 SoC

Message ID	20200821094312.3249-17-biju.das.jz@bp.renesas.com (mailing list archive)
State	Accepted
Headers	show Return-Path: <SRS0=UdsW=B7=lists.cip-project.org=bounce+64572+5191+4520428+8129116@kernel.org> DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 215D12072D From: Biju Das <biju.das.jz@bp.renesas.com> To: cip-dev@lists.cip-project.org, Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>, Pavel Machek <pavel@denx.de> Cc: Chris Paterson <chris.paterson2@renesas.com>, Biju Das <biju.das.jz@bp.renesas.com>, Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com> Subject: [cip-dev] [PATCH 16/36] arm64: defconfig: Enable R8A774E1 SoC Date: Fri, 21 Aug 2020 10:42:52 +0100 Message-Id: <20200821094312.3249-17-biju.das.jz@bp.renesas.com> In-Reply-To: <20200821094312.3249-1-biju.das.jz@bp.renesas.com> References: <20200821094312.3249-1-biju.das.jz@bp.renesas.com> Precedence: Bulk Sender: cip-dev@lists.cip-project.org Mailing-List: list cip-dev@lists.cip-project.org; contact cip-dev+owner@lists.cip-project.org Reply-To: cip-dev@lists.cip-project.org Content-Type: multipart/mixed; boundary="fPLlbtXnhffI8VOS1kq5"
Series	Add Hihope RZ/G2H basic board support \| expand [00/36] Add Hihope RZ/G2H basic board support [01/36] dt-bindings: power: Add r8a774e1 SYSC power domain definitions [02/36] dt-bindings: power: renesas,rcar-sysc: Document r8a774e1 SYSC binding [03/36] soc: renesas: rcar-sysc: Add r8a774e1 support [04/36] soc: renesas: Add Renesas R8A774E1 config option [05/36] dt-bindings: arm: renesas: Document RZ/G2H SoC DT bindings [06/36] soc: renesas: Identify RZ/G2H [07/36] dt-bindings: reset: rcar-rst: Document r8a774e1 reset module [08/36] soc: renesas: rcar-rst: Add support for RZ/G2H [09/36] clk: renesas: rcar-gen3: Add RPC clocks [10/36] clk: renesas: Add r8a774e1 CPG Core Clock Definitions [11/36] clk: renesas: rcar-gen3: Allow changing the RPC[D2] clocks [12/36] clk: renesas: cpg-mssr: Mark clocks as critical only if on at boot [13/36] clk: renesas: rzg2: Mark RWDT clocks as critical [14/36] dt-bindings: clock: renesas,cpg-mssr: Document r8a774e1 [15/36] clk: renesas: cpg-mssr: Add r8a774e1 support [16/36] arm64: defconfig: Enable R8A774E1 SoC [18/36] pinctrl: sh-pfc: r8a7795: Fix VIN versioned groups [19/36] pinctrl: sh-pfc: r8a7795-es1: Add I2C{0,3,5} pins, groups and functions [20/36] pinctrl: sh-pfc: r8a7795: Add I2C{0,3,5} pins, groups and functions [21/36] pinctrl: sh-pfc: r8a7795: Deduplicate VIN5 pin definitions [22/36] pinctrl: sh-pfc: rcar-gen3: Retain TDSELCTRL register across suspend/resume [23/36] pinctrl: sh-pfc: rcar-gen3: Rename RTS{0,1,3,4}# pin function definitions [24/36] pinctrl: sh-pfc: r8a7795-es1: Add TPU pins, groups and functions [25/36] pinctrl: sh-pfc: r8a7795: Add TPU pins, groups and functions [26/36] pinctrl: sh-pfc: r8a7795-es1: Use new macros for non-GPIO pins [27/36] pinctrl: sh-pfc: r8a7795: Use new macros for non-GPIO pins [28/36] pinctrl: sh-pfc: pfc-r8a7795-es1: Fix typo in pinmux macro for SCL3 [29/36] pinctrl: sh-pfc: pfc-r8a7795: Fix typo in pinmux macro for SCL3 [30/36] pinctrl: sh-pfc: Split R-Car H3 support in two independent drivers [31/36] dt-bindings: pinctrl: sh-pfc: Document r8a774e1 PFC support [32/36] pinctrl: sh-pfc: pfc-r8a77951: Add R8A774E1 PFC support [33/36] arm64: dts: renesas: Initial r8a774e1 SoC device tree [34/36] dt-bindings: arm: renesas: Add HopeRun RZ/G2H boards [35/36] arm64: dts: renesas: Add HiHope RZ/G2H main board support [36/36] arm64: dts: renesas: Add HiHope RZ/G2H sub board support

Commit Message

Biju Das Aug. 21, 2020, 9:42 a.m. UTC

From: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>

commit 7f8fe81eb75004dca73aa19127093977a3c8a154 upstream.

Enable the Renesas RZ/G2H (R8A774E1) SoC in the ARM64 defconfig.

Signed-off-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/1594230511-24790-6-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 arch/arm64/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

diff mbox series

Patch

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 64a116b1e98d..ef20c1f308fa 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -53,6 +53,7 @@  CONFIG_ARCH_RENESAS=y
 CONFIG_ARCH_R8A774A1=y
 CONFIG_ARCH_R8A774B1=y
 CONFIG_ARCH_R8A774C0=y
+CONFIG_ARCH_R8A774E1=y
 CONFIG_ARCH_R8A7795=y
 CONFIG_ARCH_R8A7796=y
 CONFIG_ARCH_R8A77965=y