| Message ID | 20200827145315.26261-3-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive) |
|---|---|
| State | Accepted |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | r8a774e1 add fdp1 and cpuidle support | expand |
Hi Prabhakar, On Thu, Aug 27, 2020 at 4:53 PM Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > Enable cpuidle (core shutdown) support for RZ/G2H CA5x cores. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi > +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi > @@ -127,6 +127,7 @@ > power-domains = <&sysc R8A774E1_PD_CA57_CPU0>; > next-level-cache = <&L2_CA57>; > enable-method = "psci"; > + cpu-idle-states = <&CPU_SLEEP_0>; > dynamic-power-coefficient = <854>; > clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; > operating-points-v2 = <&cluster0_opp>; > @@ -141,6 +142,7 @@ > power-domains = <&sysc R8A774E1_PD_CA57_CPU1>; > next-level-cache = <&L2_CA57>; > enable-method = "psci"; > + cpu-idle-states = <&CPU_SLEEP_0>; > clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; > operating-points-v2 = <&cluster0_opp>; > capacity-dmips-mhz = <1024>; > @@ -154,6 +156,7 @@ > power-domains = <&sysc R8A774E1_PD_CA57_CPU2>; > next-level-cache = <&L2_CA57>; > enable-method = "psci"; > + cpu-idle-states = <&CPU_SLEEP_0>; > clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; > operating-points-v2 = <&cluster0_opp>; > capacity-dmips-mhz = <1024>; > @@ -167,6 +170,7 @@ > power-domains = <&sysc R8A774E1_PD_CA57_CPU3>; > next-level-cache = <&L2_CA57>; > enable-method = "psci"; > + cpu-idle-states = <&CPU_SLEEP_1>; CPU_SLEEP_0 > clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; > operating-points-v2 = <&cluster0_opp>; > capacity-dmips-mhz = <1024>; > @@ -180,6 +184,7 @@ > power-domains = <&sysc R8A774E1_PD_CA53_CPU0>; > next-level-cache = <&L2_CA53>; > enable-method = "psci"; > + cpu-idle-states = <&CPU_SLEEP_1>; > #cooling-cells = <2>; > dynamic-power-coefficient = <277>; > clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; > @@ -194,6 +199,7 @@ > power-domains = <&sysc R8A774E1_PD_CA53_CPU1>; > next-level-cache = <&L2_CA53>; > enable-method = "psci"; > + cpu-idle-states = <&CPU_SLEEP_1>; > clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; > operating-points-v2 = <&cluster1_opp>; > capacity-dmips-mhz = <535>; > @@ -206,6 +212,7 @@ > power-domains = <&sysc R8A774E1_PD_CA53_CPU2>; > next-level-cache = <&L2_CA53>; > enable-method = "psci"; > + cpu-idle-states = <&CPU_SLEEP_1>; > clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; > operating-points-v2 = <&cluster1_opp>; > capacity-dmips-mhz = <535>; > @@ -218,6 +225,7 @@ > power-domains = <&sysc R8A774E1_PD_CA53_CPU3>; > next-level-cache = <&L2_CA53>; > enable-method = "psci"; > + cpu-idle-states = <&CPU_SLEEP_1>; > clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; > operating-points-v2 = <&cluster1_opp>; > capacity-dmips-mhz = <535>; With the above fixed: Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> No need to resend, will fix while queueing in renesas-devel for v5.10. Gr{oetje,eeting}s, Geert
diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index 34fdb9a0c325..e5445ba99e84 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -127,6 +127,7 @@ power-domains = <&sysc R8A774E1_PD_CA57_CPU0>; next-level-cache = <&L2_CA57>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; dynamic-power-coefficient = <854>; clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; operating-points-v2 = <&cluster0_opp>; @@ -141,6 +142,7 @@ power-domains = <&sysc R8A774E1_PD_CA57_CPU1>; next-level-cache = <&L2_CA57>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; operating-points-v2 = <&cluster0_opp>; capacity-dmips-mhz = <1024>; @@ -154,6 +156,7 @@ power-domains = <&sysc R8A774E1_PD_CA57_CPU2>; next-level-cache = <&L2_CA57>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0>; clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; operating-points-v2 = <&cluster0_opp>; capacity-dmips-mhz = <1024>; @@ -167,6 +170,7 @@ power-domains = <&sysc R8A774E1_PD_CA57_CPU3>; next-level-cache = <&L2_CA57>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_1>; clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; operating-points-v2 = <&cluster0_opp>; capacity-dmips-mhz = <1024>; @@ -180,6 +184,7 @@ power-domains = <&sysc R8A774E1_PD_CA53_CPU0>; next-level-cache = <&L2_CA53>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_1>; #cooling-cells = <2>; dynamic-power-coefficient = <277>; clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; @@ -194,6 +199,7 @@ power-domains = <&sysc R8A774E1_PD_CA53_CPU1>; next-level-cache = <&L2_CA53>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_1>; clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; operating-points-v2 = <&cluster1_opp>; capacity-dmips-mhz = <535>; @@ -206,6 +212,7 @@ power-domains = <&sysc R8A774E1_PD_CA53_CPU2>; next-level-cache = <&L2_CA53>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_1>; clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; operating-points-v2 = <&cluster1_opp>; capacity-dmips-mhz = <535>; @@ -218,6 +225,7 @@ power-domains = <&sysc R8A774E1_PD_CA53_CPU3>; next-level-cache = <&L2_CA53>; enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_1>; clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; operating-points-v2 = <&cluster1_opp>; capacity-dmips-mhz = <535>; @@ -236,6 +244,28 @@ cache-unified; cache-level = <2>; }; + + idle-states { + entry-method = "psci"; + + CPU_SLEEP_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010000>; + local-timer-stop; + entry-latency-us = <400>; + exit-latency-us = <500>; + min-residency-us = <4000>; + }; + + CPU_SLEEP_1: cpu-sleep-1 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010000>; + local-timer-stop; + entry-latency-us = <700>; + exit-latency-us = <700>; + min-residency-us = <5000>; + }; + }; }; extal_clk: extal {
Enable cpuidle (core shutdown) support for RZ/G2H CA5x cores. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 30 +++++++++++++++++++++++ 1 file changed, 30 insertions(+)