diff mbox series

[v2,08/18] drm/dp: Redo drm_dp_downstream_max_clock() as drm_dp_downstream_max_dotclock()

Message ID 20200904115354.25336-9-ville.syrjala@linux.intel.com (mailing list archive)
State New, archived
Headers show
Series drm/i915: Pimp DP DFP handling | expand

Commit Message

Ville Syrjala Sept. 4, 2020, 11:53 a.m. UTC 
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We want to differentiate between the DFP dotclock and TMDS clock
limits. Let's convert the current thing to just give us the
dotclock limit.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/drm_dp_helper.c         | 46 +++++++++----------------
 drivers/gpu/drm/i915/display/intel_dp.c |  4 +--
 include/drm/drm_dp_helper.h             |  4 +--
 3 files changed, 20 insertions(+), 34 deletions(-)

Comments

Lyude Paul Sept. 8, 2020, 5:56 p.m. UTC | #1 
BTW - we started using drm_dp_downstream_max_clock() in nouveau, so you'll
need to update the function call there too.

On Fri, 2020-09-04 at 14:53 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> We want to differentiate between the DFP dotclock and TMDS clock
> limits. Let's convert the current thing to just give us the
> dotclock limit.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/drm_dp_helper.c         | 46 +++++++++----------------
>  drivers/gpu/drm/i915/display/intel_dp.c |  4 +--
>  include/drm/drm_dp_helper.h             |  4 +--
>  3 files changed, 20 insertions(+), 34 deletions(-)
> 
> diff --git a/drivers/gpu/drm/drm_dp_helper.c
> b/drivers/gpu/drm/drm_dp_helper.c
> index ab87209c25d8..822a30e609ef 100644
> --- a/drivers/gpu/drm/drm_dp_helper.c
> +++ b/drivers/gpu/drm/drm_dp_helper.c
> @@ -616,41 +616,32 @@ int drm_dp_read_downstream_info(struct drm_dp_aux
> *aux,
>  EXPORT_SYMBOL(drm_dp_read_downstream_info);
>  
>  /**
> - * drm_dp_downstream_max_clock() - extract branch device max
> - *                                 pixel rate for legacy VGA
> - *                                 converter or max TMDS clock
> - *                                 rate for others
> + * drm_dp_downstream_max_dotclock() - extract downstream facing port max
> dot clock
>   * @dpcd: DisplayPort configuration data
>   * @port_cap: port capabilities
>   *
> - * See also:
> - * drm_dp_read_downstream_info()
> - * drm_dp_downstream_max_bpc()
> - *
> - * Returns: Max clock in kHz on success or 0 if max clock not defined
> + * Returns downstream facing port max dot clock in kHz on success,
> + * or 0 if max clock not defined
>   */
> -int drm_dp_downstream_max_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
> -				const u8 port_cap[4])
> +int drm_dp_downstream_max_dotclock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
> +				   const u8 port_cap[4])
>  {
> -	int type = port_cap[0] & DP_DS_PORT_TYPE_MASK;
> -	bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] &
> -		DP_DETAILED_CAP_INFO_AVAILABLE;
> +	if (!drm_dp_is_branch(dpcd))
> +		return 0;
>  
> -	if (!detailed_cap_info)
> +	if (dpcd[DP_DPCD_REV] < 0x11)
>  		return 0;
>  
> -	switch (type) {
> +	switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
>  	case DP_DS_PORT_TYPE_VGA:
> -		return port_cap[1] * 8 * 1000;
> -	case DP_DS_PORT_TYPE_DVI:
> -	case DP_DS_PORT_TYPE_HDMI:
> -	case DP_DS_PORT_TYPE_DP_DUALMODE:
> -		return port_cap[1] * 2500;
> +		if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] &
> DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
> +			return 0;
> +		return port_cap[1] * 8000;
>  	default:
>  		return 0;
>  	}
>  }
> -EXPORT_SYMBOL(drm_dp_downstream_max_clock);
> +EXPORT_SYMBOL(drm_dp_downstream_max_dotclock);
>  
>  /**
>    * drm_dp_downstream_max_bpc() - extract downstream facing port max
> @@ -793,14 +784,9 @@ void drm_dp_downstream_debug(struct seq_file *m,
>  		seq_printf(m, "\t\tSW: %d.%d\n", rev[0], rev[1]);
>  
>  	if (detailed_cap_info) {
> -		clk = drm_dp_downstream_max_clock(dpcd, port_cap);
> -
> -		if (clk > 0) {
> -			if (type == DP_DS_PORT_TYPE_VGA)
> -				seq_printf(m, "\t\tMax dot clock: %d kHz\n",
> clk);
> -			else
> -				seq_printf(m, "\t\tMax TMDS clock: %d kHz\n",
> clk);
> -		}
> +		clk = drm_dp_downstream_max_dotclock(dpcd, port_cap);
> +		if (clk > 0)
> +			seq_printf(m, "\t\tMax dot clock: %d kHz\n", clk);
>  
>  		bpc = drm_dp_downstream_max_bpc(dpcd, port_cap, edid);
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index c73b3efd84e0..8f4aee35c203 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -261,8 +261,8 @@ intel_dp_downstream_max_dotclock(struct intel_dp
> *intel_dp)
>  	if (type != DP_DS_PORT_TYPE_VGA)
>  		return max_dotclk;
>  
> -	ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd,
> -						    intel_dp-
> >downstream_ports);
> +	ds_max_dotclk = drm_dp_downstream_max_dotclock(intel_dp->dpcd,
> +						       intel_dp-
> >downstream_ports);
>  
>  	if (ds_max_dotclk != 0)
>  		max_dotclk = min(max_dotclk, ds_max_dotclk);
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index 6218de1294c1..19bc04207788 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -1643,8 +1643,8 @@ bool drm_dp_downstream_is_type(const u8
> dpcd[DP_RECEIVER_CAP_SIZE],
>  bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
>  			       const u8 port_cap[4],
>  			       const struct edid *edid);
> -int drm_dp_downstream_max_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
> -				const u8 port_cap[4]);
> +int drm_dp_downstream_max_dotclock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
> +				   const u8 port_cap[4]);
>  int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
>  			      const u8 port_cap[4],
>  			      const struct edid *edid);
diff mbox series

Patch

diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index ab87209c25d8..822a30e609ef 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -616,41 +616,32 @@  int drm_dp_read_downstream_info(struct drm_dp_aux *aux,
 EXPORT_SYMBOL(drm_dp_read_downstream_info);
 
 /**
- * drm_dp_downstream_max_clock() - extract branch device max
- *                                 pixel rate for legacy VGA
- *                                 converter or max TMDS clock
- *                                 rate for others
+ * drm_dp_downstream_max_dotclock() - extract downstream facing port max dot clock
  * @dpcd: DisplayPort configuration data
  * @port_cap: port capabilities
  *
- * See also:
- * drm_dp_read_downstream_info()
- * drm_dp_downstream_max_bpc()
- *
- * Returns: Max clock in kHz on success or 0 if max clock not defined
+ * Returns downstream facing port max dot clock in kHz on success,
+ * or 0 if max clock not defined
  */
-int drm_dp_downstream_max_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
-				const u8 port_cap[4])
+int drm_dp_downstream_max_dotclock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
+				   const u8 port_cap[4])
 {
-	int type = port_cap[0] & DP_DS_PORT_TYPE_MASK;
-	bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] &
-		DP_DETAILED_CAP_INFO_AVAILABLE;
+	if (!drm_dp_is_branch(dpcd))
+		return 0;
 
-	if (!detailed_cap_info)
+	if (dpcd[DP_DPCD_REV] < 0x11)
 		return 0;
 
-	switch (type) {
+	switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
 	case DP_DS_PORT_TYPE_VGA:
-		return port_cap[1] * 8 * 1000;
-	case DP_DS_PORT_TYPE_DVI:
-	case DP_DS_PORT_TYPE_HDMI:
-	case DP_DS_PORT_TYPE_DP_DUALMODE:
-		return port_cap[1] * 2500;
+		if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
+			return 0;
+		return port_cap[1] * 8000;
 	default:
 		return 0;
 	}
 }
-EXPORT_SYMBOL(drm_dp_downstream_max_clock);
+EXPORT_SYMBOL(drm_dp_downstream_max_dotclock);
 
 /**
   * drm_dp_downstream_max_bpc() - extract downstream facing port max
@@ -793,14 +784,9 @@  void drm_dp_downstream_debug(struct seq_file *m,
 		seq_printf(m, "\t\tSW: %d.%d\n", rev[0], rev[1]);
 
 	if (detailed_cap_info) {
-		clk = drm_dp_downstream_max_clock(dpcd, port_cap);
-
-		if (clk > 0) {
-			if (type == DP_DS_PORT_TYPE_VGA)
-				seq_printf(m, "\t\tMax dot clock: %d kHz\n", clk);
-			else
-				seq_printf(m, "\t\tMax TMDS clock: %d kHz\n", clk);
-		}
+		clk = drm_dp_downstream_max_dotclock(dpcd, port_cap);
+		if (clk > 0)
+			seq_printf(m, "\t\tMax dot clock: %d kHz\n", clk);
 
 		bpc = drm_dp_downstream_max_bpc(dpcd, port_cap, edid);
 
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index c73b3efd84e0..8f4aee35c203 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -261,8 +261,8 @@  intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
 	if (type != DP_DS_PORT_TYPE_VGA)
 		return max_dotclk;
 
-	ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd,
-						    intel_dp->downstream_ports);
+	ds_max_dotclk = drm_dp_downstream_max_dotclock(intel_dp->dpcd,
+						       intel_dp->downstream_ports);
 
 	if (ds_max_dotclk != 0)
 		max_dotclk = min(max_dotclk, ds_max_dotclk);
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 6218de1294c1..19bc04207788 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -1643,8 +1643,8 @@  bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
 bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
 			       const u8 port_cap[4],
 			       const struct edid *edid);
-int drm_dp_downstream_max_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
-				const u8 port_cap[4]);
+int drm_dp_downstream_max_dotclock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
+				   const u8 port_cap[4]);
 int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
 			      const u8 port_cap[4],
 			      const struct edid *edid);