[v4,2/3] clk: zynqmp: Use firmware specific divider clock flags

Commit Message

Amit Sunil Dhamne Sept. 9, 2020, 8:44 p.m. UTC

From: Rajan Vaja <[e-mail]>

Use ZynqMP specific divider clock flags instead of using CCF flags.

Signed-off-by: Rajan Vaja <[e-mail]>
Signed-off-by: Tejas Patel <[e-mail]>
Signed-off-by: Amit Sunil Dhamne <[e-mail]>
---
 drivers/clk/zynqmp/clk-zynqmp.h |  9 +++++++++
 drivers/clk/zynqmp/divider.c    | 25 ++++++++++++++++++++++++-
 2 files changed, 33 insertions(+), 1 deletion(-)

--
2.7.4

This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately.

Patch

diff --git a/drivers/clk/zynqmp/clk-zynqmp.h b/drivers/clk/zynqmp/clk-zynqmp.h
index 974d3da..9b2ff35e 100644
--- a/drivers/clk/zynqmp/clk-zynqmp.h
+++ b/drivers/clk/zynqmp/clk-zynqmp.h
@@ -32,6 +32,15 @@ 
 /* do not gate, ever */
 #define ZYNQMP_CLK_IS_CRITICAL         BIT(11)

+/* Type Flags for divider clock */
+#define ZYNQMP_CLK_DIVIDER_ONE_BASED           BIT(0)
+#define ZYNQMP_CLK_DIVIDER_POWER_OF_TWO                BIT(1)
+#define ZYNQMP_CLK_DIVIDER_ALLOW_ZERO          BIT(2)
+#define ZYNQMP_CLK_DIVIDER_HIWORD_MASK         BIT(3)
+#define ZYNQMP_CLK_DIVIDER_ROUND_CLOSEST       BIT(4)
+#define ZYNQMP_CLK_DIVIDER_READ_ONLY           BIT(5)
+#define ZYNQMP_CLK_DIVIDER_MAX_AT_ZERO         BIT(6)
+
 enum topology_type {
        TYPE_INVALID,
        TYPE_MUX,
diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c
index 775d54f..14adba0 100644
--- a/drivers/clk/zynqmp/divider.c
+++ b/drivers/clk/zynqmp/divider.c
@@ -283,6 +283,29 @@  static u32 zynqmp_clk_get_max_divisor(u32 clk_id, u32 type)
        return ret_payload[1];
 }

+static inline unsigned long zynqmp_clk_map_divider_ccf_flags(
+                                              const u32 zynqmp_type_flag)
+{
+       unsigned long ccf_flag = 0;
+
+       if (zynqmp_type_flag & ZYNQMP_CLK_DIVIDER_ONE_BASED)
+               ccf_flag |= CLK_DIVIDER_ONE_BASED;
+       if (zynqmp_type_flag & ZYNQMP_CLK_DIVIDER_POWER_OF_TWO)
+               ccf_flag |= CLK_DIVIDER_POWER_OF_TWO;
+       if (zynqmp_type_flag & ZYNQMP_CLK_DIVIDER_ALLOW_ZERO)
+               ccf_flag |= CLK_DIVIDER_ALLOW_ZERO;
+       if (zynqmp_type_flag & ZYNQMP_CLK_DIVIDER_POWER_OF_TWO)
+               ccf_flag |= CLK_DIVIDER_HIWORD_MASK;
+       if (zynqmp_type_flag & ZYNQMP_CLK_DIVIDER_ROUND_CLOSEST)
+               ccf_flag |= CLK_DIVIDER_ROUND_CLOSEST;
+       if (zynqmp_type_flag & ZYNQMP_CLK_DIVIDER_READ_ONLY)
+               ccf_flag |= CLK_DIVIDER_READ_ONLY;
+       if (zynqmp_type_flag & ZYNQMP_CLK_DIVIDER_MAX_AT_ZERO)
+               ccf_flag |= CLK_DIVIDER_MAX_AT_ZERO;
+
+       return ccf_flag;
+}
+
 /**
  * zynqmp_clk_register_divider() - Register a divider clock
  * @name:              Name of this clock
@@ -320,7 +343,7 @@  struct clk_hw *zynqmp_clk_register_divider(const char *name,
        /* struct clk_divider assignments */
        div->is_frac = !!((nodes->flag & CLK_FRAC) |
                          (nodes->custom_type_flag & CUSTOM_FLAG_CLK_FRAC));
-       div->flags = nodes->type_flag;
+       div->flags = zynqmp_clk_map_divider_ccf_flags(nodes->type_flag);
        div->hw.init = &init;
        div->clk_id = clk_id;
        div->div_type = nodes->type;