[PULL,03/30] target/riscv: cpu: Add a new 'resetvec' property

Commit Message

Alistair Francis Sept. 10, 2020, 6:09 p.m. UTC

From: Bin Meng <[e-mail]>

Currently the reset vector address is hard-coded in a RISC-V CPU's
instance_init() routine. In a real world we can have 2 exact same
CPUs except for the reset vector address, which is pretty common in
the RISC-V core IP licensing business.

Normally reset vector address is a configurable parameter. Let's
create a 64-bit property to store the reset vector address which
covers both 32-bit and 64-bit CPUs.

Signed-off-by: Bin Meng <[e-mail]>
Reviewed-by: Alistair Francis <[e-mail]>
Reviewed-by: Philippe Mathieu-Daudé <[e-mail]>
Message-Id: <[e-mail]>
Signed-off-by: Alistair Francis <[e-mail]>
---
 target/riscv/cpu.h | 1 +
 target/riscv/cpu.c | 1 +
 2 files changed, 2 insertions(+)

Patch

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index d3589ae6ea..0d1728a8cd 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -291,6 +291,7 @@  typedef struct RISCVCPU {
         uint16_t elen;
         bool mmu;
         bool pmp;
+        uint64_t resetvec;
     } cfg;
 } RISCVCPU;
 
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index bcdce85c5e..f6aeecac15 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -529,6 +529,7 @@  static Property riscv_cpu_properties[] = {
     DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
     DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
     DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
+    DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC),
     DEFINE_PROP_END_OF_LIST(),
 };