| Message ID | 20200910130148.8734-5-abailon@baylibre.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add support of mt8183 APU | expand |
Hi Alexandre,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on robh/for-next]
[also build test ERROR on linus/master v5.9-rc4 next-20200911]
[cannot apply to remoteproc/for-next rpmsg/for-next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Alexandre-Bailon/Add-support-of-mt8183-APU/20200911-055649
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: arm64-randconfig-r006-20200911 (attached as .config)
compiler: clang version 12.0.0 (https://github.com/llvm/llvm-project 0448d11a06b451a63a8f60408fec613ad24801ba)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install arm64 cross compiling tool for clang build
# apt-get install binutils-aarch64-linux-gnu
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=arm64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
>> Error: arch/arm64/boot/dts/mediatek/mt8183.dtsi:792.21-22 syntax error
>> FATAL ERROR: Unable to parse input tree
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index e215f1eb3eb2..28f75452961c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -967,12 +967,51 @@ ipu_adl: syscon@19010000 { #clock-cells = <1>; }; + apu0: apu@0x19100000 { + compatible = "mediatek,mt8183-apu"; + reg = <0 0x19180000 0 0x14000>; + interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_LOW>; + + iommus = <&iommu M4U_PORT_IMG_IPUO>, + <&iommu M4U_PORT_IMG_IPU3O>, + <&iommu M4U_PORT_IMG_IPUI>; + + clocks = <&ipu_core0 CLK_IPU_CORE0_AXI>, + <&ipu_core0 CLK_IPU_CORE0_IPU>, + <&ipu_core0 CLK_IPU_CORE0_JTAG>; + + clock-names = "axi", "ipu", "jtag"; + + power-domains = <&scpsys MT8183_POWER_DOMAIN_VPU_CORE0>; + status = "disabled"; + }; + ipu_core0: syscon@19180000 { compatible = "mediatek,mt8183-ipu_core0", "syscon"; reg = <0 0x19180000 0 0x1000>; #clock-cells = <1>; }; + apu1: apu@19200000 { + compatible = "mediatek,mt8183-apu"; + reg = <0 0x19280000 0 0x14000>; + interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_LOW>; + + iommus = <&iommu M4U_PORT_CAM_IPUO>, + <&iommu M4U_PORT_CAM_IPU2O>, + <&iommu M4U_PORT_CAM_IPU3O>, + <&iommu M4U_PORT_CAM_IPUI>, + <&iommu M4U_PORT_CAM_IPU2I>; + + clocks = <&ipu_core0 CLK_IPU_CORE1_AXI>, + <&ipu_core0 CLK_IPU_CORE1_IPU>, + <&ipu_core0 CLK_IPU_CORE1_JTAG>; + + clock-names = "axi", "ipu", "jtag"; + + power-domains = <&scpsys MT8183_POWER_DOMAIN_VPU_CORE1>; + }; + ipu_core1: syscon@19280000 { compatible = "mediatek,mt8183-ipu_core1", "syscon"; reg = <0 0x19280000 0 0x1000>;
This adds the support of APU to mt8183. Signed-off-by: Alexandre Bailon <abailon@baylibre.com> --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 39 ++++++++++++++++++++++++ 1 file changed, 39 insertions(+)