@@ -3997,6 +3997,13 @@ static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
int h = drm_rect_height(&plane_state->uapi.src) >> 17;
u32 offset;
+ if (INTEL_GEN(i915) >= 11)
+ max_width = icl_max_plane_width(fb, uv_plane, rotation);
+ else if (INTEL_GEN(i915) >= 10 || IS_GEMINILAKE(i915))
+ max_width = glk_max_plane_width(fb, uv_plane, rotation);
+ else
+ max_width = skl_max_plane_width(fb, uv_plane, rotation);
+
intel_add_fb_offsets(&x, &y, plane_state, uv_plane);
offset = intel_plane_compute_aligned_offset(&x, &y,
plane_state, uv_plane);
Gen 10+ and Gen11+ platforms specify different max plane width for planar formats. Add max plane width for GLK and ICL based on BSpec: 7666 Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Imre Deak <imre.deak@intel.com> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com> --- drivers/gpu/drm/i915/display/intel_display.c | 7 +++++++ 1 file changed, 7 insertions(+)