| Message ID | 20200916171653.2021483-4-John.C.Harrison@Intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/guc: Update to GuC v49 | expand |
On 9/16/2020 10:16 AM, John.C.Harrison@Intel.com wrote: > From: Matthew Brost <matthew.brost@intel.com> > > The new GuC requires the additional data structure and associated > 'private_data' pointer to be setup. This is basically a scratch area > of memory that the GuC owns. The size is read from the CSS header. > > Cc: John Harrison <john.c.harrison@intel.com> > Signed-off-by: Matthew Brost <matthew.brost@intel.com> Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Daniele > --- > drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 13 ++++++++++++- > drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 3 ++- > drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 3 +++ > drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h | 2 ++ > drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h | 6 +++++- > 5 files changed, 24 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c > index 57954c6360e0..7c16ade44b2b 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c > @@ -146,6 +146,10 @@ static void __guc_ads_init(struct intel_guc *guc) > blob->ads.gt_system_info = base + ptr_offset(blob, system_info); > blob->ads.clients_info = base + ptr_offset(blob, clients_info); > > + /* Private Data */ > + blob->ads.private_data = base + > + PAGE_ALIGN(sizeof(struct __guc_ads_blob)); > + > i915_gem_object_flush_map(guc->ads_vma->obj); > } > > @@ -158,11 +162,13 @@ static void __guc_ads_init(struct intel_guc *guc) > */ > int intel_guc_ads_create(struct intel_guc *guc) > { > - const u32 size = PAGE_ALIGN(sizeof(struct __guc_ads_blob)); > + u32 size = PAGE_ALIGN(sizeof(struct __guc_ads_blob)); > int ret; > > GEM_BUG_ON(guc->ads_vma); > > + size += PAGE_ALIGN(guc->fw.private_data_size); > + > ret = intel_guc_allocate_and_map_vma(guc, size, &guc->ads_vma, > (void **)&guc->ads_blob); > > @@ -192,4 +198,9 @@ void intel_guc_ads_reset(struct intel_guc *guc) > if (!guc->ads_vma) > return; > __guc_ads_init(guc); > + > + if (guc->fw.private_data_size) > + memset((void *)guc->ads_blob + > + PAGE_ALIGN(sizeof(struct __guc_ads_blob)), 0, > + PAGE_ALIGN(guc->fw.private_data_size)); > } > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h > index e283156624b5..fa19c9d248f2 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h > @@ -419,7 +419,8 @@ struct guc_ads { > u32 control_data; > u32 golden_context_lrca[GUC_MAX_ENGINE_CLASSES]; > u32 eng_state_size[GUC_MAX_ENGINE_CLASSES]; > - u32 reserved[16]; > + u32 private_data; > + u32 reserved[15]; > } __packed; > > /* GuC logging structures */ > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c > index 80e8b6c3bc8c..1928ce94faf8 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c > +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c > @@ -371,6 +371,9 @@ int intel_uc_fw_fetch(struct intel_uc_fw *uc_fw) > } > } > > + if (uc_fw->type == INTEL_UC_FW_TYPE_GUC) > + uc_fw->private_data_size = css->private_data_size; > + > obj = i915_gem_object_create_shmem_from_data(i915, fw->data, fw->size); > if (IS_ERR(obj)) { > err = PTR_ERR(obj); > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h > index 23d3a423ac0f..99bb1fe1af66 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h > +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h > @@ -88,6 +88,8 @@ struct intel_uc_fw { > > u32 rsa_size; > u32 ucode_size; > + > + u32 private_data_size; > }; > > #ifdef CONFIG_DRM_I915_DEBUG_GUC > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h > index 029214cdedd5..e41ffc7a7fbc 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h > +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h > @@ -69,7 +69,11 @@ struct uc_css_header { > #define CSS_SW_VERSION_UC_MAJOR (0xFF << 16) > #define CSS_SW_VERSION_UC_MINOR (0xFF << 8) > #define CSS_SW_VERSION_UC_PATCH (0xFF << 0) > - u32 reserved[14]; > + u32 reserved0[13]; > + union { > + u32 private_data_size; /* only applies to GuC */ > + u32 reserved1; > + }; > u32 header_info; > } __packed; > static_assert(sizeof(struct uc_css_header) == 128);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c index 57954c6360e0..7c16ade44b2b 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c @@ -146,6 +146,10 @@ static void __guc_ads_init(struct intel_guc *guc) blob->ads.gt_system_info = base + ptr_offset(blob, system_info); blob->ads.clients_info = base + ptr_offset(blob, clients_info); + /* Private Data */ + blob->ads.private_data = base + + PAGE_ALIGN(sizeof(struct __guc_ads_blob)); + i915_gem_object_flush_map(guc->ads_vma->obj); } @@ -158,11 +162,13 @@ static void __guc_ads_init(struct intel_guc *guc) */ int intel_guc_ads_create(struct intel_guc *guc) { - const u32 size = PAGE_ALIGN(sizeof(struct __guc_ads_blob)); + u32 size = PAGE_ALIGN(sizeof(struct __guc_ads_blob)); int ret; GEM_BUG_ON(guc->ads_vma); + size += PAGE_ALIGN(guc->fw.private_data_size); + ret = intel_guc_allocate_and_map_vma(guc, size, &guc->ads_vma, (void **)&guc->ads_blob); @@ -192,4 +198,9 @@ void intel_guc_ads_reset(struct intel_guc *guc) if (!guc->ads_vma) return; __guc_ads_init(guc); + + if (guc->fw.private_data_size) + memset((void *)guc->ads_blob + + PAGE_ALIGN(sizeof(struct __guc_ads_blob)), 0, + PAGE_ALIGN(guc->fw.private_data_size)); } diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h index e283156624b5..fa19c9d248f2 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h @@ -419,7 +419,8 @@ struct guc_ads { u32 control_data; u32 golden_context_lrca[GUC_MAX_ENGINE_CLASSES]; u32 eng_state_size[GUC_MAX_ENGINE_CLASSES]; - u32 reserved[16]; + u32 private_data; + u32 reserved[15]; } __packed; /* GuC logging structures */ diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c index 80e8b6c3bc8c..1928ce94faf8 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c @@ -371,6 +371,9 @@ int intel_uc_fw_fetch(struct intel_uc_fw *uc_fw) } } + if (uc_fw->type == INTEL_UC_FW_TYPE_GUC) + uc_fw->private_data_size = css->private_data_size; + obj = i915_gem_object_create_shmem_from_data(i915, fw->data, fw->size); if (IS_ERR(obj)) { err = PTR_ERR(obj); diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h index 23d3a423ac0f..99bb1fe1af66 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h @@ -88,6 +88,8 @@ struct intel_uc_fw { u32 rsa_size; u32 ucode_size; + + u32 private_data_size; }; #ifdef CONFIG_DRM_I915_DEBUG_GUC diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h index 029214cdedd5..e41ffc7a7fbc 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h @@ -69,7 +69,11 @@ struct uc_css_header { #define CSS_SW_VERSION_UC_MAJOR (0xFF << 16) #define CSS_SW_VERSION_UC_MINOR (0xFF << 8) #define CSS_SW_VERSION_UC_PATCH (0xFF << 0) - u32 reserved[14]; + u32 reserved0[13]; + union { + u32 private_data_size; /* only applies to GuC */ + u32 reserved1; + }; u32 header_info; } __packed; static_assert(sizeof(struct uc_css_header) == 128);