| Message ID | 20200929002929.783620-6-imre.deak@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock | expand |
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index e7b058340a1a..7968ceb23ab6 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -3026,7 +3026,15 @@ static bool icl_dp_combo_pll_clock_match(struct drm_i915_private *i915, int cloc if (clock == pll_freq) return true; - return false; + if (!tgl_combo_pll_div_frac_wa_needed(i915) || + !IS_TGL_DISP_REVID(i915, TGL_REVID_A0, TGL_REVID_C0)) + return false; + + pll_freq = skl_wrpll_calc_freq(ref_clock, + p->wrpll.dco_integer, p->wrpll.dco_fraction * 2, + pdiv, qdiv, kdiv); + + return clock == pll_freq; } static bool icl_calc_dp_combo_pll(struct intel_crtc_state *crtc_state,
The TGL A stepping and some B stepping (display C stepping) BIOSes program the combo PHY DPLL fractional divider value incorrectly, not applying the Display #22010492432 workaround. Add a workaround for such BIOS versions, so that the driver selects the correct WRPLL parameter entry correctly (selecting the same entry from the table whether or not the fractional divider was adjusted or not by BIOS according to #22010492432). Signed-off-by: Imre Deak <imre.deak@intel.com> --- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-)