@@ -288,6 +288,8 @@
#define RING_VALID_MASK 0x00000001
#define RING_VALID 0x00000001
#define RING_INVALID 0x00000000
+#define RING_WAIT_I8XX (1<<0) /* gen2, PRBx_HEAD */
+#define RING_WAIT (1<<11) /* gen3+, PRBx_CTL */
#define PRB1_TAIL 0x02040 /* 915+ only */
#define PRB1_HEAD 0x02044 /* 915+ only */
#define PRB1_START 0x02048 /* 915+ only */
@@ -2410,6 +2410,28 @@ static int i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
return 0;
}
+/*
+ * When we disable a pipe, we need to clear any pending scanline wait events
+ * to avoid hanging the ring, which we assume we are waiting on.
+ */
+static void intel_clear_scanline_wait(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+
+ if (IS_GEN2(dev)) {
+ if (I915_READ(PRB0_HEAD) & RING_WAIT_I8XX) {
+ DRM_INFO("Forcing GPU idle to flush scanline wait");
+ i915_gpu_idle(dev);
+ }
+ } else {
+ u32 tmp = I915_READ(PRB0_CTL);
+ if (tmp & RING_WAIT) {
+ I915_WRITE(PRB0_CTL, tmp);
+ POSTING_READ(PRB0_CTL);
+ }
+ }
+}
+
/**
* Sets the power management mode of the pipe and plane.
*/
@@ -2429,12 +2451,15 @@ static int intel_crtc_dpms(struct drm_crtc *crtc, int mode)
* with multiple pipes prior to enabling to new pipe.
*
* When switching off the display, make sure the cursor is
- * properly hidden prior to disabling the pipe.
+ * properly hidden and there are no pending waits prior to
+ * disabling the pipe.
*/
if (mode == DRM_MODE_DPMS_ON)
intel_update_watermarks(dev);
- else
+ else {
intel_crtc_update_cursor(crtc);
+ intel_clear_scanline_wait(dev);
+ }
dev_priv->display.dpms(crtc, mode);