From patchwork Sun Aug 8 11:01:38 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Wilson X-Patchwork-Id: 118222 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o78B2i7p018472 for ; Sun, 8 Aug 2010 11:03:20 GMT Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8CA799E75F for ; Sun, 8 Aug 2010 04:02:44 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from fireflyinternet.com (server109-228-4-14.live-servers.net [109.228.4.14]) by gabe.freedesktop.org (Postfix) with ESMTP id A87499E75F for ; Sun, 8 Aug 2010 04:02:36 -0700 (PDT) X-Default-Received-SPF: pass (skip=forwardok (res=PASS)) x-ip-name=78.156.66.37; Received: from arrandale.alporthouse.com (unverified [78.156.66.37]) by fireflyinternet.com (Firefly Internet SMTP) with ESMTP id 2384632-1500048 for multiple; Sun, 08 Aug 2010 12:02:37 +0100 From: Chris Wilson To: intel-gfx@lists.freedesktop.org Date: Sun, 8 Aug 2010 12:01:38 +0100 Message-Id: <1281265298-29757-1-git-send-email-chris@chris-wilson.co.uk> X-Mailer: git-send-email 1.7.1 X-Originating-IP: 78.156.66.37 Subject: [Intel-gfx] [PATCH] drm/i915: Clear scanline waits before disabling the pipe. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.11 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Sun, 08 Aug 2010 11:03:20 +0000 (UTC) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 97a35a4..2953b0d 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -288,6 +288,8 @@ #define RING_VALID_MASK 0x00000001 #define RING_VALID 0x00000001 #define RING_INVALID 0x00000000 +#define RING_WAIT_I8XX (1<<0) /* gen2, PRBx_HEAD */ +#define RING_WAIT (1<<11) /* gen3+, PRBx_CTL */ #define PRB1_TAIL 0x02040 /* 915+ only */ #define PRB1_HEAD 0x02044 /* 915+ only */ #define PRB1_START 0x02048 /* 915+ only */ diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 2bb3196..696767c 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -2410,6 +2410,28 @@ static int i9xx_crtc_dpms(struct drm_crtc *crtc, int mode) return 0; } +/* + * When we disable a pipe, we need to clear any pending scanline wait events + * to avoid hanging the ring, which we assume we are waiting on. + */ +static void intel_clear_scanline_wait(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + + if (IS_GEN2(dev)) { + if (I915_READ(PRB0_HEAD) & RING_WAIT_I8XX) { + DRM_INFO("Forcing GPU idle to flush scanline wait"); + i915_gpu_idle(dev); + } + } else { + u32 tmp = I915_READ(PRB0_CTL); + if (tmp & RING_WAIT) { + I915_WRITE(PRB0_CTL, tmp); + POSTING_READ(PRB0_CTL); + } + } +} + /** * Sets the power management mode of the pipe and plane. */ @@ -2429,12 +2451,15 @@ static int intel_crtc_dpms(struct drm_crtc *crtc, int mode) * with multiple pipes prior to enabling to new pipe. * * When switching off the display, make sure the cursor is - * properly hidden prior to disabling the pipe. + * properly hidden and there are no pending waits prior to + * disabling the pipe. */ if (mode == DRM_MODE_DPMS_ON) intel_update_watermarks(dev); - else + else { intel_crtc_update_cursor(crtc); + intel_clear_scanline_wait(dev); + } dev_priv->display.dpms(crtc, mode);