From patchwork Wed Jul 11 16:12:24 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dinh Nguyen X-Patchwork-Id: 1184051 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id 9D17E3FC5A for ; Wed, 11 Jul 2012 16:16:41 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1SozXN-0004Pj-2g; Wed, 11 Jul 2012 16:13:13 +0000 Received: from db3ehsobe001.messaging.microsoft.com ([213.199.154.139] helo=db3outboundpool.messaging.microsoft.com) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1SozX3-0004PK-Jo for linux-arm-kernel@lists.infradead.org; Wed, 11 Jul 2012 16:13:04 +0000 Received: from mail113-db3-R.bigfish.com (10.3.81.234) by DB3EHSOBE005.bigfish.com (10.3.84.25) with Microsoft SMTP Server id 14.1.225.23; Wed, 11 Jul 2012 16:10:16 +0000 Received: from mail113-db3 (localhost [127.0.0.1]) by mail113-db3-R.bigfish.com (Postfix) with ESMTP id 8769F120210; Wed, 11 Jul 2012 16:10:16 +0000 (UTC) X-Forefront-Antispam-Report: CIP:66.35.227.6; KIP:(null); UIP:(null); IPV:NLI; H:sj-smtp01.altera.com; RD:sj-smtp01.altera.com; EFVD:NLI X-SpamScore: 3 X-BigFish: VS3(zzc8kzz1202hzz8275bh8275dhz2fh2a8h668h839hd24he5bhf0ah107ah) Received-SPF: pass (mail113-db3: domain of altera.com designates 66.35.227.6 as permitted sender) client-ip=66.35.227.6; envelope-from=dinguyen@altera.com; helo=sj-smtp01.altera.com ; 1.altera.com ; Received: from mail113-db3 (localhost.localdomain [127.0.0.1]) by mail113-db3 (MessageSwitch) id 1342023013931077_14639; Wed, 11 Jul 2012 16:10:13 +0000 (UTC) Received: from DB3EHSMHS007.bigfish.com (unknown [10.3.81.229]) by mail113-db3.bigfish.com (Postfix) with ESMTP id DF00940047; Wed, 11 Jul 2012 16:10:13 +0000 (UTC) Received: from sj-smtp01.altera.com (66.35.227.6) by DB3EHSMHS007.bigfish.com (10.3.87.107) with Microsoft SMTP Server (TLS) id 14.1.225.23; Wed, 11 Jul 2012 16:10:13 +0000 Received: from dinguyen-VirtualBox.altera.com ([137.57.188.54]) by sj-smtp01.altera.com (8.13.7+Sun/8.13.7) with ESMTP id q6BGGr2I023042; Wed, 11 Jul 2012 09:16:58 -0700 (PDT) From: To: Subject: [PATCH v3] clocksource: dw_apb_timer: Add common DTS glue for dw_apb_timer Date: Wed, 11 Jul 2012 11:12:24 -0500 Message-ID: <1342023144-13945-1-git-send-email-dinguyen@altera.com> X-Mailer: git-send-email 1.7.9.5 MIME-Version: 1.0 X-OriginatorOrg: altera.com X-Spam-Note: CRM114 invocation failed X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [213.199.154.139 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: thomas.petazzoni@free-electrons.com, wd@denx.de, johnstul@us.ibm.com, rob.herring@calxeda.com, cytan@altera.com, Dinh Nguyen , pavel@denx.de, jamie@jamieiles.com, tglx@linutronix.de, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org From: Dinh Nguyen Make a common device tree glue for clocksource/dw_apb_timer. Move mach-picoxcell/time.c to be a generic device tree application of the dw_apb_timer. Configure mach-picoxcell to use the dw_apb_timer_of device tree implementation in drivers/clocksource. Signed-off-by: Pavel Machek Signed-off-by: Dinh Nguyen Acked-by: Jamie Iles --- Documentation/devicetree/bindings/rtc/dw-apb.txt | 24 ++++++++++ arch/arm/Kconfig | 1 + arch/arm/mach-picoxcell/Makefile | 1 - arch/arm/mach-picoxcell/common.c | 3 +- arch/arm/mach-picoxcell/common.h | 2 +- drivers/clocksource/Kconfig | 3 ++ drivers/clocksource/Makefile | 1 + .../clocksource/dw_apb_timer_of.c | 47 ++++++++++++-------- 8 files changed, 60 insertions(+), 22 deletions(-) create mode 100644 Documentation/devicetree/bindings/rtc/dw-apb.txt rename arch/arm/mach-picoxcell/time.c => drivers/clocksource/dw_apb_timer_of.c (61%) diff --git a/Documentation/devicetree/bindings/rtc/dw-apb.txt b/Documentation/devicetree/bindings/rtc/dw-apb.txt new file mode 100644 index 0000000..bbc459c --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/dw-apb.txt @@ -0,0 +1,24 @@ +* Designware APB timer + +Required properties: +- compatible: "snps,dw-apb-timer-sp" or "snps,dw-apb-timer-osc" +- reg: physical base address of the controller and length of memory mapped + region. +- interrupts: IRQ line for the timer. +- clock-frequency: The frequency in HZ of the timer. + +Example: + + timer1: timer@ffc09000 { + compatible = "snps,dw-apb-timer-sp"; + interrupts = <0 168 4>; + clock-frequency = <200000000>; + reg = <0xffc09000 0x1000>; + }; + + timer2: timer@ffd00000 { + compatible = "snps,dw-apb-timer-osc"; + interrupts = <0 169 4>; + clock-frequency = <200000000>; + reg = <0xffd00000 0x1000>; + }; diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index a91009c..57eb6ef 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -658,6 +658,7 @@ config ARCH_PICOXCELL select ARM_VIC select CPU_V6K select DW_APB_TIMER + select DW_APB_TIMER_OF select GENERIC_CLOCKEVENTS select GENERIC_GPIO select HAVE_TCM diff --git a/arch/arm/mach-picoxcell/Makefile b/arch/arm/mach-picoxcell/Makefile index e5ec4a8..8e39f80 100644 --- a/arch/arm/mach-picoxcell/Makefile +++ b/arch/arm/mach-picoxcell/Makefile @@ -1,2 +1 @@ obj-y := common.o -obj-y += time.o diff --git a/arch/arm/mach-picoxcell/common.c b/arch/arm/mach-picoxcell/common.c index a2e8ae8..8f9a0b4 100644 --- a/arch/arm/mach-picoxcell/common.c +++ b/arch/arm/mach-picoxcell/common.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include @@ -97,7 +98,7 @@ DT_MACHINE_START(PICOXCELL, "Picochip picoXcell") .nr_irqs = NR_IRQS_LEGACY, .init_irq = picoxcell_init_irq, .handle_irq = vic_handle_irq, - .timer = &picoxcell_timer, + .timer = &dw_apb_timer, .init_machine = picoxcell_init_machine, .dt_compat = picoxcell_dt_match, .restart = picoxcell_wdt_restart, diff --git a/arch/arm/mach-picoxcell/common.h b/arch/arm/mach-picoxcell/common.h index 83d55ab..a65cb02 100644 --- a/arch/arm/mach-picoxcell/common.h +++ b/arch/arm/mach-picoxcell/common.h @@ -12,6 +12,6 @@ #include -extern struct sys_timer picoxcell_timer; +extern struct sys_timer dw_apb_timer; #endif /* __PICOXCELL_COMMON_H__ */ diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index 99c6b20..e62bc7e 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -16,6 +16,9 @@ config CLKSRC_MMIO config DW_APB_TIMER bool +config DW_APB_TIMER_OF + bool + config CLKSRC_DBX500_PRCMU bool "Clocksource PRCMU Timer" depends on UX500_SOC_DB8500 diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index dd3e661..2cdaf7d 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -10,4 +10,5 @@ obj-$(CONFIG_EM_TIMER_STI) += em_sti.o obj-$(CONFIG_CLKBLD_I8253) += i8253.o obj-$(CONFIG_CLKSRC_MMIO) += mmio.o obj-$(CONFIG_DW_APB_TIMER) += dw_apb_timer.o +obj-$(CONFIG_DW_APB_TIMER_OF) += dw_apb_timer_of.o obj-$(CONFIG_CLKSRC_DBX500_PRCMU) += clksrc-dbx500-prcmu.o \ No newline at end of file diff --git a/arch/arm/mach-picoxcell/time.c b/drivers/clocksource/dw_apb_timer_of.c similarity index 61% rename from arch/arm/mach-picoxcell/time.c rename to drivers/clocksource/dw_apb_timer_of.c index 2ecba67..f07122a 100644 --- a/arch/arm/mach-picoxcell/time.c +++ b/drivers/clocksource/dw_apb_timer_of.c @@ -1,11 +1,20 @@ /* + * Copyright (C) 2012 Altera Corporation * Copyright (c) 2011 Picochip Ltd., Jamie Iles * + * Modified from mach-picoxcell/time.c + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * - * All enquiries to support@picochip.com + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . */ #include #include @@ -15,8 +24,6 @@ #include #include -#include "common.h" - static void timer_get_base_and_rate(struct device_node *np, void __iomem **base, u32 *rate) { @@ -29,7 +36,7 @@ static void timer_get_base_and_rate(struct device_node *np, panic("No clock-freq property for %s", np->name); } -static void picoxcell_add_clockevent(struct device_node *event_timer) +static void add_clockevent(struct device_node *event_timer) { void __iomem *iobase; struct dw_apb_clock_event_device *ced; @@ -49,7 +56,7 @@ static void picoxcell_add_clockevent(struct device_node *event_timer) dw_apb_clockevent_register(ced); } -static void picoxcell_add_clocksource(struct device_node *source_timer) +static void add_clocksource(struct device_node *source_timer) { void __iomem *iobase; struct dw_apb_clocksource *cs; @@ -67,55 +74,57 @@ static void picoxcell_add_clocksource(struct device_node *source_timer) static void __iomem *sched_io_base; -static u32 picoxcell_read_sched_clock(void) +static u32 read_sched_clock(void) { return __raw_readl(sched_io_base); } -static const struct of_device_id picoxcell_rtc_ids[] __initconst = { +static const struct of_device_id sptimer_ids[] __initconst = { { .compatible = "picochip,pc3x2-rtc" }, + { .compatible = "snps,dw-apb-timer-sp" }, { /* Sentinel */ }, }; -static void picoxcell_init_sched_clock(void) +static void init_sched_clock(void) { struct device_node *sched_timer; u32 rate; - sched_timer = of_find_matching_node(NULL, picoxcell_rtc_ids); + sched_timer = of_find_matching_node(NULL, sptimer_ids); if (!sched_timer) panic("No RTC for sched clock to use"); timer_get_base_and_rate(sched_timer, &sched_io_base, &rate); of_node_put(sched_timer); - setup_sched_clock(picoxcell_read_sched_clock, 32, rate); + setup_sched_clock(read_sched_clock, 32, rate); } -static const struct of_device_id picoxcell_timer_ids[] __initconst = { +static const struct of_device_id osctimer_ids[] __initconst = { { .compatible = "picochip,pc3x2-timer" }, + { .compatible = "snps,dw-apb-timer-osc" }, {}, }; -static void __init picoxcell_timer_init(void) +static void __init timer_init(void) { struct device_node *event_timer, *source_timer; - event_timer = of_find_matching_node(NULL, picoxcell_timer_ids); + event_timer = of_find_matching_node(NULL, osctimer_ids); if (!event_timer) panic("No timer for clockevent"); - picoxcell_add_clockevent(event_timer); + add_clockevent(event_timer); - source_timer = of_find_matching_node(event_timer, picoxcell_timer_ids); + source_timer = of_find_matching_node(event_timer, osctimer_ids); if (!source_timer) panic("No timer for clocksource"); - picoxcell_add_clocksource(source_timer); + add_clocksource(source_timer); of_node_put(source_timer); - picoxcell_init_sched_clock(); + init_sched_clock(); } -struct sys_timer picoxcell_timer = { - .init = picoxcell_timer_init, +struct sys_timer dw_apb_timer = { + .init = timer_init, };