@@ -2762,7 +2762,7 @@ static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
int pixel_size,
unsigned long latency_ns)
{
- long entries_required, wm_size;
+ long entries;
/*
* Note: we need to make sure we don't overflow for various clock &
@@ -2770,28 +2770,20 @@ static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
* clocks go from a few thousand to several hundred thousand.
* latency is usually a few thousand
*/
- entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
- 1000;
- entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
-
- DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
-
- wm_size = wm->fifo_size - (entries_required + wm->guard_size);
+ entries = ((clock_in_khz / 1000) * pixel_size * latency_ns) / 1000;
+ entries = DIV_ROUND_UP(entries, wm->cacheline_size);
+ entries += wm->guard_size;
- DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
+ DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries);
- /* Don't promote wm_size to unsigned... */
- if (wm_size > (long)wm->max_wm)
- wm_size = wm->max_wm;
- if (wm_size <= 0) {
- wm_size = wm->default_wm;
+ if (entries >= (long)wm->fifo_size) {
DRM_ERROR("Insufficient FIFO for plane, expect flickering:"
" entries required = %ld, available = %lu.\n",
- entries_required + wm->guard_size,
- wm->fifo_size);
+ entries, wm->fifo_size);
+ entries = wm->fifo_size - 1;
}
- return wm_size;
+ return entries;
}
struct cxsr_latency {