From patchwork Tue Jul 24 21:33:43 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 1233391 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork2.kernel.org (Postfix) with ESMTP id E32B7DF25A for ; Tue, 24 Jul 2012 21:19:37 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D20BA9F042 for ; Tue, 24 Jul 2012 14:19:37 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wg0-f43.google.com (mail-wg0-f43.google.com [74.125.82.43]) by gabe.freedesktop.org (Postfix) with ESMTP id B70259EB39 for ; Tue, 24 Jul 2012 14:17:23 -0700 (PDT) Received: by mail-wg0-f43.google.com with SMTP id dr1so21581wgb.12 for ; Tue, 24 Jul 2012 14:17:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=Z4a5HV49hqVDzKr5rWdqrzAZfTwEVr3zvCIX+mNEALE=; b=EeLP5tkGyVSHK9SQgamwMlAOl8rx5ANnXSygaCbRlM2D1X5R3EzDyH3UlttUo2L05b Bm+so+fc2FRqw7XvUAHZMUDjjnKsqsy/kCAky3eyVany1E4bdwRDOJ8VC6T4wonFmiYq xoOcu7z6j1mM3R8cF+gTbXOx73fYIH3Z4FaJA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=Z4a5HV49hqVDzKr5rWdqrzAZfTwEVr3zvCIX+mNEALE=; b=Yi7f23HrQggJRkpM0Nd8eWmDl/FXjQ10eRELBG+tMewFul6rOmFygNJyCeZ7MebE18 MlNl02WFupbiHy5/pS9I5TYki43OeH4Tti76mA66U8p+i8vZ1ftIo+4ujGVm8zf2Jkt5 nyv2wQ5sVpReQBL+WCmwYGydh4YgUyG4YI63KaefJ8yfnsoVFfmbKpJLUGh3/Efz25Bk 2IkzfBHBJ3eLEPYGW1bfgWpaSA7GYsXaVJXFHeQE/m83DShH8xKjGjryrQIbagMqgArg S7/xXj3BmNLT4My308puPR9k0LSy2XYKiHDk0Tw3Zf/yhVJPvOi4y+9v2ZWs1IU/XROn wO3w== Received: by 10.216.64.79 with SMTP id b57mr3868792wed.31.1343164643293; Tue, 24 Jul 2012 14:17:23 -0700 (PDT) Received: from hummel.ffwll.local (178-83-130-250.dynamic.hispeed.ch. [178.83.130.250]) by mx.google.com with ESMTPS id cl8sm6258845wib.10.2012.07.24.14.17.22 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 24 Jul 2012 14:17:22 -0700 (PDT) From: Daniel Vetter To: Intel Graphics Development Date: Tue, 24 Jul 2012 23:33:43 +0200 Message-Id: <1343165630-21604-3-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1343165630-21604-1-git-send-email-daniel.vetter@ffwll.ch> References: <1343165630-21604-1-git-send-email-daniel.vetter@ffwll.ch> X-Gm-Message-State: ALoCoQmmN4fsijQkTX1FtI1i25ul+15Q4QnLNZ57DIHygATgi6LLN1EPGnibIDtMzX4p7cEb6cP1 Cc: Daniel Vetter Subject: [Intel-gfx] [PATCH 2/9] drm/i915: properly guard ilk ips state X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org The update_gfx_val function called from mark_busy wasn't taking the mchdev_lock, as it should have. Also sprinkle a few spinlock asserts over the code to document things better. Things are still rather confusing, especially since a few variables in dev_priv are used by both the gen6+ rps code and the ilk ips code. But protected by totally different locks. Follow-on patches will clean that up. v2: Don't add a deadlock ... hence split up update_gfx_val into a wrapper that grabs the lock and an internal __ variant for callsites within intel_pm.c that already have taken the lock. Signed-Off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_pm.c | 50 ++++++++++++++++++++++++++------------- 1 file changed, 34 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index b6e8fbf..21a0088 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -2693,6 +2693,21 @@ static const struct cparams { { 0, 800, 231, 23784 }, }; +/** + * Lock protecting IPS related data structures + * - i915_mch_dev + * - dev_priv->max_delay + * - dev_priv->min_delay + * - dev_priv->fmax + * - dev_priv->gpu_busy + * - dev_priv->gfx_power + */ +static DEFINE_SPINLOCK(mchdev_lock); + +/* Global for IPS driver to get at the current i915 device. Protected by + * mchdev_lock. */ +static struct drm_i915_private *i915_mch_dev; + unsigned long i915_chipset_val(struct drm_i915_private *dev_priv) { u64 total_count, diff, ret; @@ -2700,6 +2715,8 @@ unsigned long i915_chipset_val(struct drm_i915_private *dev_priv) unsigned long now = jiffies_to_msecs(jiffies), diff1; int i; + assert_spin_locked(&mchdev_lock); + diff1 = now - dev_priv->last_time1; /* Prevent division-by-zero if we are asking too fast. @@ -2901,15 +2918,14 @@ static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid) return v_table[pxvid].vd; } -void i915_update_gfx_val(struct drm_i915_private *dev_priv) +void __i915_update_gfx_val(struct drm_i915_private *dev_priv) { struct timespec now, diff1; u64 diff; unsigned long diffms; u32 count; - if (dev_priv->info->gen != 5) - return; + assert_spin_locked(&mchdev_lock); getrawmonotonic(&now); diff1 = timespec_sub(now, dev_priv->last_time2); @@ -2937,11 +2953,25 @@ void i915_update_gfx_val(struct drm_i915_private *dev_priv) dev_priv->gfx_power = diff; } +void i915_update_gfx_val(struct drm_i915_private *dev_priv) +{ + if (dev_priv->info->gen != 5) + return; + + spin_lock(&mchdev_lock); + + __i915_update_gfx_val(dev_priv); + + spin_unlock(&mchdev_lock); +} + unsigned long i915_gfx_val(struct drm_i915_private *dev_priv) { unsigned long t, corr, state1, corr2, state2; u32 pxvid, ext_v; + assert_spin_locked(&mchdev_lock); + pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->cur_delay * 4)); pxvid = (pxvid >> 24) & 0x7f; ext_v = pvid_to_extvid(dev_priv, pxvid); @@ -2967,23 +2997,11 @@ unsigned long i915_gfx_val(struct drm_i915_private *dev_priv) state2 = (corr2 * state1) / 10000; state2 /= 100; /* convert to mW */ - i915_update_gfx_val(dev_priv); + __i915_update_gfx_val(dev_priv); return dev_priv->gfx_power + state2; } -/* Global for IPS driver to get at the current i915 device */ -static struct drm_i915_private *i915_mch_dev; -/* - * Lock protecting IPS related data structures - * - i915_mch_dev - * - dev_priv->max_delay - * - dev_priv->min_delay - * - dev_priv->fmax - * - dev_priv->gpu_busy - */ -static DEFINE_SPINLOCK(mchdev_lock); - /** * i915_read_mch_val - return value for IPS use *