From patchwork Wed Jul 25 12:51:44 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 1237351 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id DA1423FD4F for ; Wed, 25 Jul 2012 12:53:15 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 96FC7A0A67 for ; Wed, 25 Jul 2012 05:53:15 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-bk0-f49.google.com (mail-bk0-f49.google.com [209.85.214.49]) by gabe.freedesktop.org (Postfix) with ESMTP id 1FB06A0A67 for ; Wed, 25 Jul 2012 05:51:53 -0700 (PDT) Received: by bkcji2 with SMTP id ji2so495682bkc.36 for ; Wed, 25 Jul 2012 05:51:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=y5Eew14sGuCRn0SJ8P8Fjhwjnsbdj0HTXNrs0TAB/yY=; b=EMWVCqbmMkyiMivv6JlsN+RAdMcZHnjGXPWmffCfSJ2uYSu6pFTrYL+GmFQ29+KUlU zXoRIURMA8HotaNL6ZCyxT2XZPQV0oXwCSuRgM7tsh7CMwqqIs1/+XSV9EGumlHYrDBe X1E+G1iN/DnBIhgVI9Of2iYYaXNEly9kMPWhc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=y5Eew14sGuCRn0SJ8P8Fjhwjnsbdj0HTXNrs0TAB/yY=; b=gY4crygawhDmZn3gI/I2lNcQIkYsek8u1a95qWoZfCpGXwU0wU3St8+EYowZEja2Sh o1vsU1tTSlZBPvl+I2zBxem5TCDREjXaz9pC1ex0CTNwFcyA0Cfo6LmWN6Z+0O7s8Mnu heIePQqPWglqjqh+YaG389XX9TSdWpY7Uwa39iZMkvrTkkk5kYf8q9t5OO7pFhC0Lo7p W7gxVuDjlf5Si39o65i8GyH1bYHShjNGobj16dXCTpe9s93QYQTyQQdYG5Lqgo5RiWr5 d/glwXsSpKGzDESooWr9gIXnW6QJz1N7HcGMOQFyFapLeR50PTsR8vEggFwaNrkX89hw Bl+w== Received: by 10.204.152.19 with SMTP id e19mr11994892bkw.8.1343220712986; Wed, 25 Jul 2012 05:51:52 -0700 (PDT) Received: from aaron.ffwll.local (178-83-130-250.dynamic.hispeed.ch. [178.83.130.250]) by mx.google.com with ESMTPS id 14sm12786595bkq.12.2012.07.25.05.51.51 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 25 Jul 2012 05:51:52 -0700 (PDT) From: Daniel Vetter To: Intel Graphics Development Date: Wed, 25 Jul 2012 14:51:44 +0200 Message-Id: <1343220704-4210-2-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1343220704-4210-1-git-send-email-daniel.vetter@ffwll.ch> References: <1342803748-25695-1-git-send-email-chris@chris-wilson.co.uk> <1343220704-4210-1-git-send-email-daniel.vetter@ffwll.ch> X-Gm-Message-State: ALoCoQm5tivYVbzpth0I+6sux0iVM7MeHuKa2Em4W4fNzSq80K9f8Zvub35466HnpwfIxXC51krh Cc: Daniel Vetter Subject: [Intel-gfx] [PATCH 2/2] drm/i915: disable indirect state pointers in render flush X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Since we don't guarantee that objects stay at the same gtt offset, userspace needs to reload all indirect state anyway, even with hw contexts. The hw provides a little pipe_control flag to disable at least some these indirect state pointers and hence avoid to save/restore them at context switch time. Seems to improve hw context switch throughput as measured by running glxgears by about 0.5%, barely above the noise on my ivb gt2 here. Signed-Off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_ringbuffer.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index f52778f..bc95142 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -228,6 +228,7 @@ gen6_render_ring_flush(struct intel_ring_buffer *ring, flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; + flags |= PIPE_CONTROL_INDIRECT_STATE_DISABLE; if (IS_GEN7(ring->dev)) flags |= PIPE_CONTROL_DC_CACHE_FLUSH; /*