From patchwork Thu Jul 26 14:09:44 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 1242791 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork2.kernel.org (Postfix) with ESMTP id 019E6E0038 for ; Thu, 26 Jul 2012 14:10:15 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BCF70A0E88 for ; Thu, 26 Jul 2012 07:10:14 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-bk0-f49.google.com (mail-bk0-f49.google.com [209.85.214.49]) by gabe.freedesktop.org (Postfix) with ESMTP id 86DAE9E793 for ; Thu, 26 Jul 2012 07:09:39 -0700 (PDT) Received: by bkcji2 with SMTP id ji2so1310479bkc.36 for ; Thu, 26 Jul 2012 07:09:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=mQzdKBH9zl14t+xabJ5mWxZAfgXiqmSqJUe/mJqCCyg=; b=NJdrYis2zCoFJkFfcC7g7lfdB076uop3ARKXWms7CwYuvNn/BFoTJDefr4SswW00Ed F7tod8O5JUbdow9UJjTWW7PI0jXs7r8xJiu182QZ1UGbi/jHAApkYfUg9dExLx+LBguJ QwOYUthPEZ6en45J6sN0rF04Yk5/H9zUhqpZE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=mQzdKBH9zl14t+xabJ5mWxZAfgXiqmSqJUe/mJqCCyg=; b=RTKy94HrSc5Pu4c51/C0TrQUmFWjvJP0Pw/4BIWztMOcSWAfAuM8SF4FGfWKijuTKA /tHMGkwLt4ZKwn2tABziE0P+X9K6kl49BQ7duZM1sQDaMdDOzZd6F5I7GUvoWbgHc2bG fCcUve/3eB4gfBkKtiXS+KZvB0QaYRI/TOqiqwa5KfOpY5SJkUyuVL420N/macK2O3sd /VdgQAjBIS7aluBK5GmHWkej8FV7GPzJObj0CQoxqbmouc8j+TBWAFdts1Rm50QmwurX pYimZK/TkIkpSv97xpjXi9fQK4Ce2gN9D5MDRhqXsiHPm3Q0D5wR8RuhVYp0a1rvEHpk Q2uw== Received: by 10.205.134.133 with SMTP id ic5mr14332161bkc.15.1343311778483; Thu, 26 Jul 2012 07:09:38 -0700 (PDT) Received: from phenom.ffwll.local (178-83-130-250.dynamic.hispeed.ch. [178.83.130.250]) by mx.google.com with ESMTPS id he8sm14679258bkc.3.2012.07.26.07.09.36 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 26 Jul 2012 07:09:37 -0700 (PDT) From: Daniel Vetter To: Intel Graphics Development , Carsten Emde Date: Thu, 26 Jul 2012 16:09:44 +0200 Message-Id: <1343311784-27048-1-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <501074AA.1070905@osadl.org> References: <501074AA.1070905@osadl.org> X-Gm-Message-State: ALoCoQmwUzgH6yX6ggc4KNu2qCHc1tV9k7VDz4z0WWA2nPUUDrIsIyAooOaR72eKhdeNHbUGvivU Cc: Daniel Vetter Subject: [Intel-gfx] [PATCH] drm/i915 disable combination mode X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org ... but this time around don't forget to save/restore the lbpc reg. v2: Actually try to restroe LBPC on resume. v3: _Really_ try to git add. --- Hi Carsten, Please test this quick hack, afaict that should be more towards the ultimate truth of gen4 backlight heaven than adding random invert brightness quirks. Yours, Daniel --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_reg.h | 3 +++ drivers/gpu/drm/i915/i915_suspend.c | 10 ++++++++++ drivers/gpu/drm/i915/intel_panel.c | 4 ++-- 4 files changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 0b2eb17..f483ef4 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -507,6 +507,7 @@ typedef struct drm_i915_private { /* Register state */ bool modeset_on_lid; u8 saveLBB; + u8 saveLBPC; u32 saveDSPACNTR; u32 saveDSPBCNTR; u32 saveDSPARB; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 1310caa..29ccd22 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1882,6 +1882,9 @@ #define PFIT_AUTO_RATIOS 0x61238 +/* legacy/combination backlight modes in the pci config space */ +#define PCI_LBPC 0xf4 + /* Backlight control */ #define BLC_PWM_CTL2 0x61250 /* 965+ only */ #define BLM_PWM_ENABLE (1 << 31) diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c index 740c076..7f44079 100644 --- a/drivers/gpu/drm/i915/i915_suspend.c +++ b/drivers/gpu/drm/i915/i915_suspend.c @@ -641,6 +641,11 @@ static void i915_save_display(struct drm_device *dev) dev_priv->saveLVDS = I915_READ(LVDS); } + if (IS_GEN2(dev) || IS_GEN4(dev)) { + pci_read_config_byte(dev->pdev, PCI_LBPC, + &dev_priv->saveLBPC); + } + if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev)) dev_priv->savePFIT_CONTROL = I915_READ(PFIT_CONTROL); @@ -758,6 +763,11 @@ static void i915_restore_display(struct drm_device *dev) I915_WRITE(PP_CONTROL, dev_priv->savePP_CONTROL); } + if (IS_GEN2(dev) || IS_GEN4(dev)) { + pci_write_config_byte(dev->pdev, PCI_LBPC, + dev_priv->saveLBPC); + } + /* Display Port state */ if (SUPPORTS_INTEGRATED_DP(dev)) { I915_WRITE(DP_B, dev_priv->saveDP_B); diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c index 10c7d39..c8b6bc5 100644 --- a/drivers/gpu/drm/i915/intel_panel.c +++ b/drivers/gpu/drm/i915/intel_panel.c @@ -33,8 +33,6 @@ #include #include "intel_drv.h" -#define PCI_LBPC 0xf4 /* legacy/combination backlight modes */ - void intel_fixed_panel_mode(struct drm_display_mode *fixed_mode, struct drm_display_mode *adjusted_mode) @@ -121,11 +119,13 @@ static int is_backlight_combination_mode(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; +#if 0 if (INTEL_INFO(dev)->gen >= 4) return I915_READ(BLC_PWM_CTL2) & BLM_COMBINATION_MODE; if (IS_GEN2(dev)) return I915_READ(BLC_PWM_CTL) & BLM_LEGACY_MODE; +#endif return 0; }