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[RFC,10/30] drm/i915: add DP support to intel_ddi_disable_port

Message ID 1346191621-12996-11-git-send-email-przanoni@gmail.com (mailing list archive)
State RFC
Headers show

Commit Message

Paulo Zanoni Aug. 28, 2012, 10:06 p.m. UTC 
From: Paulo Zanoni <paulo.r.zanoni@intel.com>

Just a missing register. There is no problem to run this code when the
output is HDMI.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)
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Patch

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index dd28e35..fed7856 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -961,15 +961,25 @@  static void intel_ddi_disable_port(struct drm_i915_private *dev_priv,
 				   enum port port)
 {
 	uint32_t reg, val;
+	bool wait = false;
 
 	reg = DDI_BUF_CTL(port);
 	val = I915_READ(reg);
 	if (val & DDI_BUF_CTL_ENABLE) {
 		val &= ~DDI_BUF_CTL_ENABLE;
 		I915_WRITE(reg, val);
-		intel_wait_ddi_buf_idle(dev_priv, port);
+		wait = true;
 	}
 
+	reg = DP_TP_CTL(port);
+	val = I915_READ(reg);
+	val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
+	val |= DP_TP_CTL_LINK_TRAIN_PAT1;
+	I915_WRITE(reg, val);
+
+	if (wait)
+		intel_wait_ddi_buf_idle(dev_priv, port);
+
 	switch (I915_READ(PORT_CLK_SEL(port))) {
 	case PORT_CLK_SEL_WRPLL1:
 		reg = WRPLL_CTL1;