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[09/24] ARM: ixp4xx: use __iomem pointers for MMIO

Message ID 1347658492-11608-10-git-send-email-arnd@arndb.de (mailing list archive)
State New, archived
Headers show

Commit Message

Arnd Bergmann Sept. 14, 2012, 9:34 p.m. UTC
ARM is moving to stricter checks on readl/write functions,
so we need to use the correct types everywhere.

At the moment, this patch conflicts with other patches in linux-next,
need to sort this out.

Cc: Imre Kaloz <kaloz@openwrt.org>
Cc: Krzysztof Halasa <khc@pm.waw.pl>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
 arch/arm/mach-ixp4xx/common.c                   |    2 +-
 arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h |    8 ++++----
 2 files changed, 5 insertions(+), 5 deletions(-)

Comments

Krzysztof Halasa Sept. 18, 2012, 10:31 a.m. UTC | #1
Arnd Bergmann <arnd@arndb.de> writes:

> ARM is moving to stricter checks on readl/write functions,
> so we need to use the correct types everywhere.
>
> At the moment, this patch conflicts with other patches in linux-next,
> need to sort this out.

Very nice, I will take care of these 3 patches.
Krzysztof Halasa Sept. 18, 2012, 7:22 p.m. UTC | #2
Krzysztof Halasa <khc@pm.waw.pl> writes:

>> At the moment, this patch conflicts with other patches in linux-next,
>> need to sort this out.
>
> Very nice, I will take care of these 3 patches.

I mean, just this one IXP4xx patch :-)
Krzysztof Halasa Sept. 18, 2012, 8:12 p.m. UTC | #3
Actually, there are some minor problems here (both patches merged,
ixp4xx only):

Arnd Bergmann <arnd@arndb.de> writes:

> --- a/arch/arm/mach-ixp4xx/include/mach/cpu.h
> +++ b/arch/arm/mach-ixp4xx/include/mach/cpu.h
> @@ -37,7 +38,7 @@
>  
>  static inline u32 ixp4xx_read_feature_bits(void)
>  {
> -	u32 val = ~*IXP4XX_EXP_CFG2;
> +	u32 val = ~__raw_readl(IXP4XX_EXP_CFG2);
>  

This is all fine, but

> @@ -51,7 +52,7 @@ static inline u32 ixp4xx_read_feature_bits(void)
>  
>  static inline void ixp4xx_write_feature_bits(u32 value)
>  {
> -	*IXP4XX_EXP_CFG2 = ~value;
> +	__raw_writel(~cpu_to_le32(value), IXP4XX_EXP_CFG2);
>  }

The EXP_CFG2 register is already in host order, no need for
cpu_to_le32() as the replaced code clearly shows.

Can you merge both IXP4xx parts (in the two patches) and fix the above,
please? Thanks.
Arnd Bergmann Sept. 18, 2012, 9:25 p.m. UTC | #4
On Tuesday 18 September 2012, Krzysztof Halasa wrote:
> > @@ -51,7 +52,7 @@ static inline u32 ixp4xx_read_feature_bits(void)
> >  
> >  static inline void ixp4xx_write_feature_bits(u32 value)
> >  {
> > -     *IXP4XX_EXP_CFG2 = ~value;
> > +     __raw_writel(~cpu_to_le32(value), IXP4XX_EXP_CFG2);
> >  }
> 
> The EXP_CFG2 register is already in host order, no need for
> cpu_to_le32() as the replaced code clearly shows.
> 
> Can you merge both IXP4xx parts (in the two patches) and fix the above,
> please? Thanks.

Thanks for pointing this out, that was a mistake on my end, because I first
tried to convert to writel, with byteswap and then made up my mind and used
__raw_writel instead because it seemed silly to do two byteswaps.

	Arnd
diff mbox

Patch

diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
index 8c9cd5d..fdf91a1 100644
--- a/arch/arm/mach-ixp4xx/common.c
+++ b/arch/arm/mach-ixp4xx/common.c
@@ -70,7 +70,7 @@  static struct map_desc ixp4xx_io_desc[] __initdata = {
 	},
 #ifdef CONFIG_DEBUG_LL
 	{	/* Debug UART mapping */
-		.virtual	= IXP4XX_DEBUG_UART_BASE_VIRT,
+		.virtual	= (unsigned long)IXP4XX_DEBUG_UART_BASE_VIRT,
 		.pfn		= __phys_to_pfn(IXP4XX_DEBUG_UART_BASE_PHYS),
 		.length		= IXP4XX_DEBUG_UART_REGION_SIZE,
 		.type		= MT_DEVICE
diff --git a/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h b/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h
index 2272f5a..eb68b61 100644
--- a/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h
+++ b/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h
@@ -49,21 +49,21 @@ 
  * Expansion BUS Configuration registers
  */
 #define IXP4XX_EXP_CFG_BASE_PHYS	(0xC4000000)
-#define IXP4XX_EXP_CFG_BASE_VIRT	(0xFFBFE000)
+#define IXP4XX_EXP_CFG_BASE_VIRT	IOMEM(0xFFBFE000)
 #define IXP4XX_EXP_CFG_REGION_SIZE	(0x00001000)
 
 /*
  * PCI Config registers
  */
 #define IXP4XX_PCI_CFG_BASE_PHYS	(0xC0000000)
-#define	IXP4XX_PCI_CFG_BASE_VIRT	(0xFFBFF000)
+#define	IXP4XX_PCI_CFG_BASE_VIRT	IOMEM(0xFFBFF000)
 #define IXP4XX_PCI_CFG_REGION_SIZE	(0x00001000)
 
 /*
  * Peripheral space
  */
 #define IXP4XX_PERIPHERAL_BASE_PHYS	(0xC8000000)
-#define IXP4XX_PERIPHERAL_BASE_VIRT	(0xFFBEB000)
+#define IXP4XX_PERIPHERAL_BASE_VIRT	IOMEM(0xFFBEB000)
 #define IXP4XX_PERIPHERAL_REGION_SIZE	(0x00013000)
 
 /*
@@ -73,7 +73,7 @@ 
  * aligned so that it * can be used with the low-level debug code.
  */
 #define	IXP4XX_DEBUG_UART_BASE_PHYS	(0xC8000000)
-#define	IXP4XX_DEBUG_UART_BASE_VIRT	(0xffb00000)
+#define	IXP4XX_DEBUG_UART_BASE_VIRT	IOMEM(0xffb00000)
 #define	IXP4XX_DEBUG_UART_REGION_SIZE	(0x00001000)
 
 #define IXP4XX_EXP_CS0_OFFSET	0x00