diff mbox

[v2,4/9] drm/i915: Program correct m n tu register for Valleyview

Message ID 1348753389-30736-5-git-send-email-vijay.a.purushothaman@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Vijay Purushothaman Sept. 27, 2012, 1:43 p.m. UTC 
m n tu register offset has changed in Valleyview. Also fixed DP limit
frequencies.

Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |    6 +++---
 drivers/gpu/drm/i915/intel_dp.c      |    5 +++++
 2 files changed, 8 insertions(+), 3 deletions(-)

Comments

Jesse Barnes Sept. 27, 2012, 3:18 p.m. UTC | #1 
On Thu, 27 Sep 2012 19:13:04 +0530
Vijay Purushothaman <vijay.a.purushothaman@intel.com> wrote:

> m n tu register offset has changed in Valleyview. Also fixed DP limit
> frequencies.
> 
> Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
> Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c |    6 +++---
>  drivers/gpu/drm/i915/intel_dp.c      |    5 +++++
>  2 files changed, 8 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 947c97d..68828e7 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -393,10 +393,10 @@ static const intel_limit_t intel_limits_vlv_hdmi = {
>  };
>  
>  static const intel_limit_t intel_limits_vlv_dp = {
> -	.dot = { .min = 162000, .max = 270000 },
> -	.vco = { .min = 5994000, .max = 4000000 },
> +	.dot = { .min = 25000, .max = 270000 },
> +	.vco = { .min = 4000000, .max = 6000000 },
>  	.n = { .min = 1, .max = 7 },
> -	.m = { .min = 60, .max = 300 }, /* guess */
> +	.m = { .min = 22, .max = 450 },
>  	.m1 = { .min = 2, .max = 3 },
>  	.m2 = { .min = 11, .max = 156 },
>  	.p = { .min = 10, .max = 30 },
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index de8092a..c111c3f 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -804,6 +804,11 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
>  		I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
>  		I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
>  		I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
> +	} else if (IS_VALLEYVIEW(dev)) {
> +		I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
> +		I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
> +		I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
> +		I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
>  	} else {
>  		I915_WRITE(PIPE_GMCH_DATA_M(pipe),
>  			   ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |

Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 947c97d..68828e7 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -393,10 +393,10 @@  static const intel_limit_t intel_limits_vlv_hdmi = {
 };
 
 static const intel_limit_t intel_limits_vlv_dp = {
-	.dot = { .min = 162000, .max = 270000 },
-	.vco = { .min = 5994000, .max = 4000000 },
+	.dot = { .min = 25000, .max = 270000 },
+	.vco = { .min = 4000000, .max = 6000000 },
 	.n = { .min = 1, .max = 7 },
-	.m = { .min = 60, .max = 300 }, /* guess */
+	.m = { .min = 22, .max = 450 },
 	.m1 = { .min = 2, .max = 3 },
 	.m2 = { .min = 11, .max = 156 },
 	.p = { .min = 10, .max = 30 },
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index de8092a..c111c3f 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -804,6 +804,11 @@  intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
 		I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
 		I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
 		I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
+	} else if (IS_VALLEYVIEW(dev)) {
+		I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
+		I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
+		I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
+		I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
 	} else {
 		I915_WRITE(PIPE_GMCH_DATA_M(pipe),
 			   ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |