From patchwork Fri Jan 9 12:02:36 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 1575 Received: from vger.kernel.org (vger.kernel.org [209.132.176.167]) by demeter.kernel.org (8.14.2/8.14.2) with ESMTP id n09CDjea013717 for ; Fri, 9 Jan 2009 04:13:45 -0800 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752842AbZAIMRX (ORCPT ); Fri, 9 Jan 2009 07:17:23 -0500 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1752875AbZAIMRX (ORCPT ); Fri, 9 Jan 2009 07:17:23 -0500 Received: from tx2ehsobe005.messaging.microsoft.com ([65.55.88.15]:17597 "EHLO TX2EHSOBE009.bigfish.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752842AbZAIMRW (ORCPT ); Fri, 9 Jan 2009 07:17:22 -0500 X-Greylist: delayed 902 seconds by postgrey-1.27 at vger.kernel.org; Fri, 09 Jan 2009 07:17:22 EST Received: from mail62-tx2-R.bigfish.com (10.9.14.241) by TX2EHSOBE009.bigfish.com (10.9.40.29) with Microsoft SMTP Server id 8.1.291.1; Fri, 9 Jan 2009 12:02:19 +0000 Received: from mail62-tx2 (localhost.localdomain [127.0.0.1]) by mail62-tx2-R.bigfish.com (Postfix) with ESMTP id 3009C11D8125; Fri, 9 Jan 2009 12:02:19 +0000 (UTC) X-BigFish: VPS3(zzzzzzz32i43j) Received: by mail62-tx2 (MessageSwitch) id 1231502535829308_13845; Fri, 9 Jan 2009 12:02:15 +0000 (UCT) Received: from ausb3extmailp01.amd.com (unknown [163.181.251.8]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail62-tx2.bigfish.com (Postfix) with ESMTP id 805C3F3804D; Fri, 9 Jan 2009 12:02:15 +0000 (UTC) Received: from ausb3twp02.amd.com ([163.181.250.38]) by ausb3extmailp01.amd.com (Switch-3.2.7/Switch-3.2.7) with ESMTP id n09C29qB001054; Fri, 9 Jan 2009 06:02:12 -0600 X-WSS-ID: 0KD7DFH-02-OQL-01 Received: from sausexbh2.amd.com (SAUSEXBH2.amd.com [163.181.22.102]) by ausb3twp02.amd.com (Tumbleweed MailGate 3.5.1) with ESMTP id 20B9216A0434; Fri, 9 Jan 2009 06:02:05 -0600 (CST) Received: from sausexmb2.amd.com ([163.181.3.157]) by sausexbh2.amd.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 9 Jan 2009 06:02:10 -0600 Received: from SDRSEXMB1.amd.com ([172.20.3.116]) by sausexmb2.amd.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 9 Jan 2009 06:02:10 -0600 Received: from localhost.localdomain ([165.204.85.48]) by SDRSEXMB1.amd.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 9 Jan 2009 13:02:07 +0100 From: Andre Przywara To: avi@redhat.com CC: kvm@vger.kernel.org, Andre Przywara Subject: [PATCH] kvm: always set accessed bit in VMCS segment selectors Date: Fri, 9 Jan 2009 13:02:36 +0100 Message-ID: <1231502556706-git-send-email-andre.przywara@amd.com> X-Mailer: git-send-email 1.5.2.2 X-OriginalArrivalTime: 09 Jan 2009 12:02:07.0861 (UTC) FILETIME=[18602A50:01C97252] MIME-Version: 1.0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Intel manual 22.3.1.2 demands that the accessed bit (bit 0 in type field) must be set when on DS,ES,FS and GS when the selector is usable. This fixes cross vendor migration from AMD to Intel. I am not sure what the real purpose of this check is, so I put this in the VMX path and not in the SVM one. If someone has an explanation which justifies a move, I am happy to do this. Signed-off-by: Andre Przywara --- arch/x86/kvm/vmx.c | 5 +++++ 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c index 9b56d21..d19e39c 100644 --- a/arch/x86/kvm/vmx.c +++ b/arch/x86/kvm/vmx.c @@ -1723,6 +1723,11 @@ static void vmx_set_segment(struct kvm_vcpu *vcpu, ar = 0xf3; } else ar = vmx_segment_access_rights(var); + + /* 22.3.1.2 demands that the accessed bit must be set on [DEFG]S */ + if (var->s && (sf->ar_bytes & AR_UNUSABLE_MASK) == 0) + ar |= 0x1; + vmcs_write32(sf->ar_bytes, ar); }