diff mbox

drm/i915: don't implement WaDisableEarlyCull for Haswell

Message ID 1349903399-4417-1-git-send-email-przanoni@gmail.com (mailing list archive)
State New, archived
Headers show

Commit Message

Paulo Zanoni Oct. 10, 2012, 9:09 p.m. UTC 
From: Paulo Zanoni <paulo.r.zanoni@intel.com>

Introduced in commit 87f8020ec9e3069597746040a4e8655189bc0c1a:
  drm/i915: implement WaDisableEarlyCull for VLV and IVB

Notice that the original patch sent to the mailing list did not
include the Haswell chunk, it was added later.

The bit set by the commit does not exist on Haswell machines (at least
that's what the documentation says). Also, the commit gives me a GPU
hang every time we're loading the driver. So let's revert the Haswell
chunk, making the patch do only what its title actually says.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 4 ----
 1 file changed, 4 deletions(-)

Comments

Lespiau, Damien Oct. 10, 2012, 9:42 p.m. UTC | #1 
On Wed, Oct 10, 2012 at 10:09 PM, Paulo Zanoni <przanoni@gmail.com> wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> Introduced in commit 87f8020ec9e3069597746040a4e8655189bc0c1a:
>   drm/i915: implement WaDisableEarlyCull for VLV and IVB
>
> Notice that the original patch sent to the mailing list did not
> include the Haswell chunk, it was added later.
>
> The bit set by the commit does not exist on Haswell machines (at least
> that's what the documentation says). Also, the commit gives me a GPU
> hang every time we're loading the driver. So let's revert the Haswell
> chunk, making the patch do only what its title actually says.
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

Indeed the bit definition has disappeared in the documentation, but
the wa is listed in the wa database. A hang is very handy to decide
who is right :)

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Daniel Vetter Oct. 10, 2012, 9:46 p.m. UTC | #2 
On Wed, Oct 10, 2012 at 10:42:52PM +0100, Lespiau, Damien wrote:
> On Wed, Oct 10, 2012 at 10:09 PM, Paulo Zanoni <przanoni@gmail.com> wrote:
> > From: Paulo Zanoni <paulo.r.zanoni@intel.com>
> >
> > Introduced in commit 87f8020ec9e3069597746040a4e8655189bc0c1a:
> >   drm/i915: implement WaDisableEarlyCull for VLV and IVB
> >
> > Notice that the original patch sent to the mailing list did not
> > include the Haswell chunk, it was added later.
> >
> > The bit set by the commit does not exist on Haswell machines (at least
> > that's what the documentation says). Also, the commit gives me a GPU
> > hang every time we're loading the driver. So let's revert the Haswell
> > chunk, making the patch do only what its title actually says.
> >
> > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> 
> Indeed the bit definition has disappeared in the documentation, but
> the wa is listed in the wa database. A hang is very handy to decide
> who is right :)
> 
> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Queued for -next, thanks for the patch.
-Daniel
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index eb757e5..07da990 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3470,10 +3470,6 @@  static void haswell_init_clock_gating(struct drm_device *dev)
 	 */
 	I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
 
-	/* WaDisableEarlyCull */
-	I915_WRITE(_3D_CHICKEN3,
-		   _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
-
 	/* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
 	I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
 		   GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);