[2/5] drm/i915: implement WaDisableRenderCachePipelinedFlush
diff mbox

Message ID 1350553794-5534-3-git-send-email-daniel.vetter@ffwll.ch
State New, archived
Headers show

Commit Message

Daniel Vetter Oct. 18, 2012, 9:49 a.m. UTC
Comment says for eaglelake/cantiga, but it's listed in the ilk table,
too. So apply it to both.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/i915_reg.h |    1 +
 drivers/gpu/drm/i915/intel_pm.c |    8 ++++++++
 2 files changed, 9 insertions(+)

Comments

Chris Wilson Oct. 18, 2012, 11:21 a.m. UTC | #1
On Thu, 18 Oct 2012 11:49:51 +0200, Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
> Comment says for eaglelake/cantiga, but it's listed in the ilk table,
> too. So apply it to both.
> 
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

Looks harmless due to the massive number of other p/c errata and that
pipelined render cache flushes have never been relied upon.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
Daniel Vetter Oct. 29, 2012, 9:33 p.m. UTC | #2
On Thu, Oct 18, 2012 at 12:21:17PM +0100, Chris Wilson wrote:
> On Thu, 18 Oct 2012 11:49:51 +0200, Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
> > Comment says for eaglelake/cantiga, but it's listed in the ilk table,
> > too. So apply it to both.
> > 
> > Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> 
> Looks harmless due to the massive number of other p/c errata and that
> pipelined render cache flushes have never been relied upon.
> 
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>

I've queued the first two here for -next (since they don't seem to fix any
reported bugs).
-Daniel

Patch
diff mbox

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a4162dd..1970c54 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -661,6 +661,7 @@ 
 #define   MI_ARB_DISPLAY_PRIORITY_B_A		(1 << 0)	/* display B > display A */
 
 #define CACHE_MODE_0	0x02120 /* 915+ only */
+#define   CM0_PIPELINED_RENDER_FLUSH_DISABLE (1<<8)
 #define   CM0_IZ_OPT_DISABLE      (1<<6)
 #define   CM0_ZR_OPT_DISABLE      (1<<5)
 #define	  CM0_STC_EVICT_DISABLE_LRA_SNB	(1<<5)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 72f41aa..aa77639 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3397,6 +3397,10 @@  static void ironlake_init_clock_gating(struct drm_device *dev)
 	I915_WRITE(_3D_CHICKEN2,
 		   _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
 		   _3D_CHICKEN2_WM_READ_PIPELINED);
+
+	/* WaDisableRenderCachePipelinedFlush */
+	I915_WRITE(CACHE_MODE_0,
+		   _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
 }
 
 static void gen6_init_clock_gating(struct drm_device *dev)
@@ -3728,6 +3732,10 @@  static void g4x_init_clock_gating(struct drm_device *dev)
 	if (IS_GM45(dev))
 		dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
 	I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
+
+	/* WaDisableRenderCachePipelinedFlush */
+	I915_WRITE(CACHE_MODE_0,
+		   _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
 }
 
 static void crestline_init_clock_gating(struct drm_device *dev)