From patchwork Thu Oct 18 12:44:35 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 1610161 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id A2A6E3FC1A for ; Thu, 18 Oct 2012 12:43:47 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 89D6E9EA03 for ; Thu, 18 Oct 2012 05:43:47 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wg0-f43.google.com (mail-wg0-f43.google.com [74.125.82.43]) by gabe.freedesktop.org (Postfix) with ESMTP id C7AFA9E8CF for ; Thu, 18 Oct 2012 05:43:37 -0700 (PDT) Received: by mail-wg0-f43.google.com with SMTP id dq11so5791361wgb.12 for ; Thu, 18 Oct 2012 05:43:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=from:to:cc:subject:date:message-id:x-mailer; bh=XYeyLi76hTaQKxosEbiQzF6mEEGLL0saVk+C/yEYL6g=; b=ayVvZeoCn9byMFRc9XSCvjdc7hmmbozzT4CMs6nh8wC1sxKhG8xMHY2pihZ2j/Zd75 jzxle9Zs6CH3Pd/o5s+l7X6N273XOPWtu5R1iWQ5LG611pWyDPhuNi+xjF/Z0bPqAYtH FMWeFv8J7KAgOhnnUDbaywCHyW18I+aqSZo+o= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:x-gm-message-state; bh=XYeyLi76hTaQKxosEbiQzF6mEEGLL0saVk+C/yEYL6g=; b=lHkwc6tjz7bhHIfJiSaUmuZzIn0tT+1YzmtvIbyMnZVtAVDynaE3VxmUGiuQBLjcyd Q7iuyVjhNcqHW80T0OfsDGZNHoMwiH1SFUerD3ce3gZJHbla167vKlqwZ8Yfi7r99eaV RbaqGCeM+ghFLGCHUeXZrVyZbZtDNruJS7r6n3ogJi6hfOw5WrDX2zwQwJ5lvP5D4R1n y4RDbzjKPfqAI8AX5KD3YkVeL5xZnwR+8+flhvqm2lcZV/pXv31ZIQCABqXaO0ekLB3P Cg9HibkoKn7AcQF9e2MP1xhUohRS4cdYL+ZUbosvkvnHh/RBc2kDFGV2FWLHEr1gZmp0 qdpg== Received: by 10.216.144.69 with SMTP id m47mr13137364wej.183.1350564216942; Thu, 18 Oct 2012 05:43:36 -0700 (PDT) Received: from phenom.ffwll.local (178-83-130-250.dynamic.hispeed.ch. [178.83.130.250]) by mx.google.com with ESMTPS id a10sm33414091wiz.4.2012.10.18.05.43.36 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 18 Oct 2012 05:43:36 -0700 (PDT) From: Daniel Vetter To: Intel Graphics Development Date: Thu, 18 Oct 2012 14:44:35 +0200 Message-Id: <1350564275-27885-1-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.7.10.4 X-Gm-Message-State: ALoCoQnVd85N8bBv7i9mbSwOBQxyqTBprXDcBoXAGxDEOSCoGsBNWRutU8lWHDG+VynaRG9q3pt/ Cc: Daniel Vetter Subject: [Intel-gfx] [PATCH] drm/i915: unconditionally use mt forcewake on hsw/ivb X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Single-threaded forcewake was only used on some early pre-production ivybridge machines, all the latest ones should use mt forcewake. And we already assume this in other places of the code (e.g. DERRMR support in the ddx, or the latest intel_gt_reset patch to reset any lingering forcewake references left behind by the bios), so don't bother here, too. Signed-off-by: Daniel Vetter Reviewed-by: Mika Kuoppala Reviewed-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_pm.c | 31 ++++--------------------------- 1 file changed, 4 insertions(+), 27 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 2b3cddf..568c98d 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4146,35 +4146,12 @@ void intel_gt_init(struct drm_device *dev) if (IS_VALLEYVIEW(dev)) { dev_priv->gt.force_wake_get = vlv_force_wake_get; dev_priv->gt.force_wake_put = vlv_force_wake_put; - } else if (INTEL_INFO(dev)->gen >= 6) { + } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { + dev_priv->gt.force_wake_get = __gen6_gt_force_wake_mt_get; + dev_priv->gt.force_wake_put = __gen6_gt_force_wake_mt_put; + } else if (IS_GEN6(dev)) { dev_priv->gt.force_wake_get = __gen6_gt_force_wake_get; dev_priv->gt.force_wake_put = __gen6_gt_force_wake_put; - - /* IVB configs may use multi-threaded forcewake */ - if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { - u32 ecobus; - - /* A small trick here - if the bios hasn't configured - * MT forcewake, and if the device is in RC6, then - * force_wake_mt_get will not wake the device and the - * ECOBUS read will return zero. Which will be - * (correctly) interpreted by the test below as MT - * forcewake being disabled. - */ - mutex_lock(&dev->struct_mutex); - __gen6_gt_force_wake_mt_get(dev_priv); - ecobus = I915_READ_NOTRACE(ECOBUS); - __gen6_gt_force_wake_mt_put(dev_priv); - mutex_unlock(&dev->struct_mutex); - - if (ecobus & FORCEWAKE_MT_ENABLE) { - DRM_DEBUG_KMS("Using MT version of forcewake\n"); - dev_priv->gt.force_wake_get = - __gen6_gt_force_wake_mt_get; - dev_priv->gt.force_wake_put = - __gen6_gt_force_wake_mt_put; - } - } } }