[7/8] drm/i915: PIPE_CONTROL TLB invalidate requires CS stall
diff mbox

Message ID 1350583639-773-7-git-send-email-jbarnes@virtuousgeek.org
State New, archived
Headers show

Commit Message

Jesse Barnes Oct. 18, 2012, 6:07 p.m. UTC
"If ENABLED, PIPE_CONTROL command will flush the in flight data  written
out by render engine to Global Observation point on flush done. Also
Requires stall bit ([20] of DW1) set."

So set the stall bit to ensure proper invalidation.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
 drivers/gpu/drm/i915/intel_ringbuffer.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Chris Wilson Oct. 23, 2012, 11:42 a.m. UTC | #1
On Thu, 18 Oct 2012 13:07:18 -0500, Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> "If ENABLED, PIPE_CONTROL command will flush the in flight data  written
> out by render engine to Global Observation point on flush done. Also
> Requires stall bit ([20] of DW1) set."

That quotation doesn't make sense in the context of TLB invalidation,
and the programming guide here very carefully avoids the mention of
requiring any stall bit set for the post-sync op of TLB invalidation.

Maybe quote chapter and verse as well?
-Chris
Jesse Barnes Oct. 25, 2012, 6:28 p.m. UTC | #2
On Tue, 23 Oct 2012 12:42:07 +0100
Chris Wilson <chris@chris-wilson.co.uk> wrote:

> On Thu, 18 Oct 2012 13:07:18 -0500, Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> > "If ENABLED, PIPE_CONTROL command will flush the in flight data  written
> > out by render engine to Global Observation point on flush done. Also
> > Requires stall bit ([20] of DW1) set."
> 
> That quotation doesn't make sense in the context of TLB invalidation,
> and the programming guide here very carefully avoids the mention of
> requiring any stall bit set for the post-sync op of TLB invalidation.
> 
> Maybe quote chapter and verse as well?

I thought the "Also Requires stall bit ([20] of DW1) set." was pretty
clear?

Patch
diff mbox

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index e7daa90..1e09c62 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -246,7 +246,7 @@  gen6_render_ring_flush(struct intel_ring_buffer *ring,
 		/*
 		 * TLB invalidate requires a post-sync write.
 		 */
-		flags |= PIPE_CONTROL_QW_WRITE;
+		flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
 	}
 
 	ret = intel_ring_begin(ring, 4);