| Message ID | 1351085683-3649-1-git-send-email-przanoni@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com> On Wed, Oct 24, 2012 at 11:34 AM, Paulo Zanoni <przanoni@gmail.com> wrote: > From: Paulo Zanoni <paulo.r.zanoni@intel.com> > > See the documentation for the DDI_FUNC_CTL register, EDP Input Select > bits: when the EDP input selection is B, the VTOTAL_B must be > programmed with the VTOTAL_EDP value, same thing for selection C. > > V2: Use I915_READ as suggested by Daniel Vetter. > > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> > --- > drivers/gpu/drm/i915/intel_display.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 1b72f36..8379e12 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -4524,6 +4524,14 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc, > (adjusted_mode->crtc_vsync_start - 1) | > ((adjusted_mode->crtc_vsync_end - 1) << 16)); > > + /* Workaround: when the EDP input selection is B, the VTOTAL_B must be > + * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is > + * documented on the DDI_FUNC_CTL register description, EDP Input Select > + * bits. */ > + if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && > + (pipe == PIPE_B || pipe == PIPE_C)) > + I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); > + > /* pipesrc controls the size that is scaled from, which should > * always be the user's requested size. > */ > -- > 1.7.11.4 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 1b72f36..8379e12 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -4524,6 +4524,14 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc, (adjusted_mode->crtc_vsync_start - 1) | ((adjusted_mode->crtc_vsync_end - 1) << 16)); + /* Workaround: when the EDP input selection is B, the VTOTAL_B must be + * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is + * documented on the DDI_FUNC_CTL register description, EDP Input Select + * bits. */ + if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && + (pipe == PIPE_B || pipe == PIPE_C)) + I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); + /* pipesrc controls the size that is scaled from, which should * always be the user's requested size. */