From patchwork Mon Sep 13 22:35:09 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 176092 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id o8DMdSKT012499 for ; Mon, 13 Sep 2010 22:39:48 GMT Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4E2249EB0B for ; Mon, 13 Sep 2010 15:39:28 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail.ffwll.ch (cable-static-49-187.intergga.ch [157.161.49.187]) by gabe.freedesktop.org (Postfix) with ESMTP id 9B2E69EAFD for ; Mon, 13 Sep 2010 15:33:44 -0700 (PDT) Received: by mail.ffwll.ch (Postfix, from userid 1000) id DBA5120C219; Tue, 14 Sep 2010 00:36:05 +0200 (CEST) X-Spam-ASN: X-Spam-Checker-Version: SpamAssassin 3.2.5 (2008-06-10) on orange.ffwll.ch X-Spam-Level: X-Spam-Hammy: 0.000-+--H*UA:git-send-email, 0.000-+--H*x:git-send-email, 0.000-+--1.7.1 X-Spam-Status: No, score=-4.4 required=6.0 tests=ALL_TRUSTED,AWL,BAYES_00 autolearn=ham version=3.2.5 X-Spam-Spammy: 0.961-+--H*r:mail.ffwll.ch, 0.958-+--H*m:ffwll Received: from viiv.ffwll.ch (viiv.ffwll.ch [192.168.23.128]) by mail.ffwll.ch (Postfix) with ESMTP id 27D2220C236; Tue, 14 Sep 2010 00:35:26 +0200 (CEST) Received: from daniel by viiv.ffwll.ch with local (Exim 4.72) (envelope-from ) id 1OvHcT-0008Mq-U7; Tue, 14 Sep 2010 00:35:25 +0200 From: Daniel Vetter To: intel-gfx@lists.freedesktop.org Date: Tue, 14 Sep 2010 00:35:09 +0200 Message-Id: <1284417314-32070-13-git-send-email-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1284417314-32070-1-git-send-email-daniel.vetter@ffwll.ch> References: <1284417314-32070-1-git-send-email-daniel.vetter@ffwll.ch> Cc: Daniel Vetter Subject: [Intel-gfx] [PATCH 12/17] intel-gtt: move chipset flush to the gtt driver struct X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.11 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter1.kernel.org [140.211.167.41]); Mon, 13 Sep 2010 22:39:49 +0000 (UTC) diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c index 8e149a8..e6d69ef 100644 --- a/drivers/char/agp/intel-gtt.c +++ b/drivers/char/agp/intel-gtt.c @@ -81,6 +81,7 @@ struct intel_gtt_driver { * For chipsets that need to support old ums (non-gem) code, this * needs to be identical to the various supported agp memory types! */ bool (*check_flags)(unsigned int flags); + void (*chipset_flush)(void); }; static struct _intel_private { @@ -840,7 +841,7 @@ static void intel_i830_setup_flush(void) * that buffer out, we just fill 1KB and clflush it out, on the assumption * that it'll push whatever was in there out. It appears to work. */ -static void intel_i830_chipset_flush(struct agp_bridge_data *bridge) +static void i830_chipset_flush(void) { unsigned int *pg = intel_private.i8xx_flush_page; @@ -1063,6 +1064,11 @@ static int intel_fake_agp_remove_entries(struct agp_memory *mem, return 0; } +static void intel_fake_agp_chipset_flush(struct agp_bridge_data *bridge) +{ + intel_private.driver->chipset_flush(); +} + static struct agp_memory *intel_fake_agp_alloc_by_type(size_t pg_count, int type) { @@ -1164,7 +1170,7 @@ static void intel_i9xx_setup_flush(void) "can't ioremap flush page - no chipset flushing\n"); } -static void intel_i915_chipset_flush(struct agp_bridge_data *bridge) +static void i9xx_chipset_flush(void) { if (intel_private.i9xx_flush_page) writel(1, intel_private.i9xx_flush_page); @@ -1291,7 +1297,7 @@ static const struct agp_bridge_driver intel_830_driver = { .agp_alloc_pages = agp_generic_alloc_pages, .agp_destroy_page = agp_generic_destroy_page, .agp_destroy_pages = agp_generic_destroy_pages, - .chipset_flush = intel_i830_chipset_flush, + .chipset_flush = intel_fake_agp_chipset_flush, }; static const struct agp_bridge_driver intel_915_driver = { @@ -1314,7 +1320,7 @@ static const struct agp_bridge_driver intel_915_driver = { .agp_alloc_pages = agp_generic_alloc_pages, .agp_destroy_page = agp_generic_destroy_page, .agp_destroy_pages = agp_generic_destroy_pages, - .chipset_flush = intel_i915_chipset_flush, + .chipset_flush = intel_fake_agp_chipset_flush, }; static const struct agp_bridge_driver intel_i965_driver = { @@ -1337,7 +1343,7 @@ static const struct agp_bridge_driver intel_i965_driver = { .agp_alloc_pages = agp_generic_alloc_pages, .agp_destroy_page = agp_generic_destroy_page, .agp_destroy_pages = agp_generic_destroy_pages, - .chipset_flush = intel_i915_chipset_flush, + .chipset_flush = intel_fake_agp_chipset_flush, }; static const struct agp_bridge_driver intel_gen6_driver = { @@ -1360,7 +1366,7 @@ static const struct agp_bridge_driver intel_gen6_driver = { .agp_alloc_pages = agp_generic_alloc_pages, .agp_destroy_page = agp_generic_destroy_page, .agp_destroy_pages = agp_generic_destroy_pages, - .chipset_flush = intel_i915_chipset_flush, + .chipset_flush = intel_fake_agp_chipset_flush, }; static const struct agp_bridge_driver intel_g33_driver = { @@ -1383,7 +1389,7 @@ static const struct agp_bridge_driver intel_g33_driver = { .agp_alloc_pages = agp_generic_alloc_pages, .agp_destroy_page = agp_generic_destroy_page, .agp_destroy_pages = agp_generic_destroy_pages, - .chipset_flush = intel_i915_chipset_flush, + .chipset_flush = intel_fake_agp_chipset_flush, }; static const struct intel_gtt_driver i81x_gtt_driver = { @@ -1394,6 +1400,7 @@ static const struct intel_gtt_driver i8xx_gtt_driver = { .setup = i830_setup, .write_entry = i830_write_entry, .check_flags = i830_check_flags, + .chipset_flush = i830_chipset_flush, }; static const struct intel_gtt_driver i915_gtt_driver = { .gen = 3, @@ -1401,6 +1408,7 @@ static const struct intel_gtt_driver i915_gtt_driver = { /* i945 is the last gpu to need phys mem (for overlay and cursors). */ .write_entry = i830_write_entry, .check_flags = i830_check_flags, + .chipset_flush = i9xx_chipset_flush, }; static const struct intel_gtt_driver g33_gtt_driver = { .gen = 3, @@ -1408,6 +1416,7 @@ static const struct intel_gtt_driver g33_gtt_driver = { .setup = i9xx_setup, .write_entry = i965_write_entry, .check_flags = i830_check_flags, + .chipset_flush = i9xx_chipset_flush, }; static const struct intel_gtt_driver pineview_gtt_driver = { .gen = 3, @@ -1415,18 +1424,21 @@ static const struct intel_gtt_driver pineview_gtt_driver = { .setup = i9xx_setup, .write_entry = i965_write_entry, .check_flags = i830_check_flags, + .chipset_flush = i9xx_chipset_flush, }; static const struct intel_gtt_driver i965_gtt_driver = { .gen = 4, .setup = i9xx_setup, .write_entry = i965_write_entry, .check_flags = i830_check_flags, + .chipset_flush = i9xx_chipset_flush, }; static const struct intel_gtt_driver g4x_gtt_driver = { .gen = 5, .setup = i9xx_setup, .write_entry = i965_write_entry, .check_flags = i830_check_flags, + .chipset_flush = i9xx_chipset_flush, }; static const struct intel_gtt_driver ironlake_gtt_driver = { .gen = 5, @@ -1434,12 +1446,14 @@ static const struct intel_gtt_driver ironlake_gtt_driver = { .setup = i9xx_setup, .write_entry = i965_write_entry, .check_flags = i830_check_flags, + .chipset_flush = i9xx_chipset_flush, }; static const struct intel_gtt_driver sandybridge_gtt_driver = { .gen = 6, .setup = i9xx_setup, .write_entry = gen6_write_entry, .check_flags = gen6_check_flags, + .chipset_flush = i9xx_chipset_flush, }; /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of