From patchwork Sun Jan 11 21:39:44 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 1816 Received: from vger.kernel.org (vger.kernel.org [209.132.176.167]) by demeter.kernel.org (8.14.2/8.14.2) with ESMTP id n0BLaAON018760 for ; Sun, 11 Jan 2009 13:36:11 -0800 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753019AbZAKVj2 (ORCPT ); Sun, 11 Jan 2009 16:39:28 -0500 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1752924AbZAKVj2 (ORCPT ); Sun, 11 Jan 2009 16:39:28 -0500 Received: from outbound-va3.frontbridge.com ([216.32.180.16]:47925 "EHLO VA3EHSOBE002.bigfish.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752709AbZAKVjZ (ORCPT ); Sun, 11 Jan 2009 16:39:25 -0500 Received: from mail9-va3-R.bigfish.com (10.7.14.246) by VA3EHSOBE002.bigfish.com (10.7.40.22) with Microsoft SMTP Server id 8.1.291.1; Sun, 11 Jan 2009 21:39:24 +0000 Received: from mail9-va3 (localhost.localdomain [127.0.0.1]) by mail9-va3-R.bigfish.com (Postfix) with ESMTP id 418D91C9009B; Sun, 11 Jan 2009 21:39:24 +0000 (UTC) X-BigFish: VPS1(zzzzzzz32i62h) X-Spam-TCS-SCL: 1:0 X-FB-SS: 5, Received: by mail9-va3 (MessageSwitch) id 1231709962701891_3479; Sun, 11 Jan 2009 21:39:22 +0000 (UCT) Received: from ausb3extmailp02.amd.com (ausb3extmailp02.amd.com [163.181.251.22]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail9-va3.bigfish.com (Postfix) with ESMTP id 92810FB8056; Sun, 11 Jan 2009 21:39:22 +0000 (UTC) Received: from ausb3twp02.amd.com ([163.181.250.38]) by ausb3extmailp02.amd.com (Switch-3.2.7/Switch-3.2.7) with ESMTP id n0BLdIka024228; Sun, 11 Jan 2009 15:39:21 -0600 X-WSS-ID: 0KDBTH7-02-9S0-01 Received: from sausexbh1.amd.com (sausexbh1.amd.com [163.181.22.101]) by ausb3twp02.amd.com (Tumbleweed MailGate 3.5.1) with ESMTP id 2E54F16A043F; Sun, 11 Jan 2009 15:39:06 -0600 (CST) Received: from sausexmb1.amd.com ([163.181.3.156]) by sausexbh1.amd.com with Microsoft SMTPSVC(6.0.3790.3959); Sun, 11 Jan 2009 15:39:17 -0600 Received: from SDRSEXMB1.amd.com ([172.20.3.116]) by sausexmb1.amd.com with Microsoft SMTPSVC(6.0.3790.3959); Sun, 11 Jan 2009 15:39:17 -0600 Received: from localhost.localdomain ([165.204.85.48]) by SDRSEXMB1.amd.com with Microsoft SMTPSVC(6.0.3790.3959); Sun, 11 Jan 2009 22:39:15 +0100 From: Andre Przywara To: avi@redhat.com CC: Amit Shah , kvm@vger.kernel.org, Andre Przywara Subject: [PATCH] kvm: set accessed bit for VMCB segment selectors Date: Sun, 11 Jan 2009 22:39:44 +0100 Message-ID: <1231709984808-git-send-email-andre.przywara@amd.com> X-Mailer: git-send-email 1.5.2.2 In-Reply-To: <20090110051748.GB24354@amit-x200.pnq.redhat.com> References: <20090110051748.GB24354@amit-x200.pnq.redhat.com> X-OriginalArrivalTime: 11 Jan 2009 21:39:15.0579 (UTC) FILETIME=[0CEE1CB0:01C97435] MIME-Version: 1.0 Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org In the segment descriptor _cache_ the accessed bit is always set (although it can be cleared in the descriptor itself). Since Intel checks for this condition on a VMENTRY, set this bit in the AMD path to enable cross vendor migration. Signed-off-by: Andre Przywara Acked-By: Amit Shah --- arch/x86/kvm/svm.c | 41 +++++++++++++++++++++++++++++------------ 1 files changed, 29 insertions(+), 12 deletions(-) diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c index 14e517e..41ba356 100644 --- a/arch/x86/kvm/svm.c +++ b/arch/x86/kvm/svm.c @@ -793,20 +793,37 @@ static void svm_get_segment(struct kvm_vcpu *vcpu, var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1; var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1; - /* - * SVM always stores 0 for the 'G' bit in the CS selector in - * the VMCB on a VMEXIT. This hurts cross-vendor migration: - * Intel's VMENTRY has a check on the 'G' bit. - */ - if (seg == VCPU_SREG_CS) + switch (seg) { + case VCPU_SREG_CS: + /* + * SVM always stores 0 for the 'G' bit in the CS selector in + * the VMCB on a VMEXIT. This hurts cross-vendor migration: + * Intel's VMENTRY has a check on the 'G' bit. + */ var->g = s->limit > 0xfffff; - - /* - * Work around a bug where the busy flag in the tr selector - * isn't exposed - */ - if (seg == VCPU_SREG_TR) + break; + case VCPU_SREG_TR: + /* + * Work around a bug where the busy flag in the tr selector + * isn't exposed + */ var->type |= 0x2; + break; + case VCPU_SREG_DS: + case VCPU_SREG_ES: + case VCPU_SREG_FS: + case VCPU_SREG_GS: + /* + * The accessed bit must always be set in the segment + * descriptor cache, although it can be cleared in the + * descriptor, the cached bit always remains at 1. Since + * Intel has a check on this, set it here to support + * cross-vendor migration. + */ + if (!var->unusable) + var->type |= 0x1; + break; + } var->unusable = !var->present; }