[3/3] ARM: MM: Add the workaround of Errata 766421
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Message ID 001901cdd669$4cd77070$e6865150$%kim@samsung.com
State New, archived
Headers show

Commit Message

boojin.kim Dec. 10, 2012, midnight UTC
This patch adds the workaround of errata 766421 that adds 'dmb' when changing
the translation regime after conditions that the errata 766421 may occur.
Concretely, Add 'dmb' when changing ASID and secure state for cortex-A15 r0p4.

Signed-off-by: Boojin Kim <boojin.kim@samsung.com>
---
 arch/arm/Kconfig             |   13 +++++++++++++
 arch/arm/mach-exynos/Kconfig |    1 +
 arch/arm/mm/proc-v7-2level.S |    2 ++
 3 files changed, 16 insertions(+), 0 deletions(-)

--
1.7.5.4

Comments

Rob Herring Dec. 12, 2012, 9:15 p.m. UTC | #1
On 12/09/2012 06:00 PM, Boojin Kim wrote:
> This patch adds the workaround of errata 766421 that adds 'dmb' when changing
> the translation regime after conditions that the errata 766421 may occur.
> Concretely, Add 'dmb' when changing ASID and secure state for cortex-A15 r0p4.
> 
> Signed-off-by: Boojin Kim <boojin.kim@samsung.com>
> ---
>  arch/arm/Kconfig             |   13 +++++++++++++
>  arch/arm/mach-exynos/Kconfig |    1 +
>  arch/arm/mm/proc-v7-2level.S |    2 ++
>  3 files changed, 16 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 93397da..9bd34dd 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -1417,6 +1417,19 @@ config ARM_ERRATA_775420
>  	 to deadlock. This workaround puts DSB before executing ISB if
>  	 an abort may occur on cache maintenance.
> 
> +config ARM_ERRATA_766421
> +	bool "ARM errata: Strongly-Ordered/Device load or NC LDREX could return incorrect data"
> +	depends on CPU_V7
> +	help
> +	  This option enables the workaround for the erratum 766421 affecting
> +	  Cortex-A15 erratum (r0p4).
> +	  In certain situations, a strongly ordered or device load instruction,
> +	  or a non-cacheable normal memory load-exclusive instruction could
> +	  match multiple fill buffers and return incorrect data.
> +	  This workaround is add DMB instruction when making any change to the
> +	  translation regime and before doing any new loads/stores/preloads
> +	  in the new translation regime.
> +
>  config ARM_ERRATA_773022
>  	bool "ARM errata: incorrect instructions may be executed from loop buffer"
>  	depends on CPU_V7
> diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
> index bb92f4c..4e28e1c 100644
> --- a/arch/arm/mach-exynos/Kconfig
> +++ b/arch/arm/mach-exynos/Kconfig
> @@ -66,6 +66,7 @@ config SOC_EXYNOS5250
>  	select S5P_PM if PM
>  	select S5P_SLEEP if PM
>  	select SAMSUNG_DMADEV
> +	select ARM_ERRATA_766421
>  	help
>  	  Enable EXYNOS5250 SoC support
> 
> diff --git a/arch/arm/mm/proc-v7-2level.S b/arch/arm/mm/proc-v7-2level.S
> index fd045e7..c663b2e 100644
> --- a/arch/arm/mm/proc-v7-2level.S
> +++ b/arch/arm/mm/proc-v7-2level.S
> @@ -53,6 +53,8 @@ ENTRY(cpu_v7_switch_mm)
>  #endif
>  #ifdef CONFIG_ARM_ERRATA_754322
>  	dsb
> +#elif CONFIG_ARM_ERRATA_766421
> +	dmb

Despite the comments on the 1st patch, this one would still be needed as
it cannot be done before the kernel runs.

However, if you have 754322 and 766421 enabled, we would have dsb and
dmb. We do something like this instead:

#if defined(CONFIG_ARM_ERRATA_754322) || defined(CONFIG_ARM_ERRATA_766421)
  	dsb
#endif

Rob

>  #endif
>  	mcr	p15, 0, r1, c13, c0, 1		@ set context ID
>  	isb
> --
> 1.7.5.4
> 
> 
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>

Patch
diff mbox

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 93397da..9bd34dd 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1417,6 +1417,19 @@  config ARM_ERRATA_775420
 	 to deadlock. This workaround puts DSB before executing ISB if
 	 an abort may occur on cache maintenance.

+config ARM_ERRATA_766421
+	bool "ARM errata: Strongly-Ordered/Device load or NC LDREX could return incorrect data"
+	depends on CPU_V7
+	help
+	  This option enables the workaround for the erratum 766421 affecting
+	  Cortex-A15 erratum (r0p4).
+	  In certain situations, a strongly ordered or device load instruction,
+	  or a non-cacheable normal memory load-exclusive instruction could
+	  match multiple fill buffers and return incorrect data.
+	  This workaround is add DMB instruction when making any change to the
+	  translation regime and before doing any new loads/stores/preloads
+	  in the new translation regime.
+
 config ARM_ERRATA_773022
 	bool "ARM errata: incorrect instructions may be executed from loop buffer"
 	depends on CPU_V7
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index bb92f4c..4e28e1c 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -66,6 +66,7 @@  config SOC_EXYNOS5250
 	select S5P_PM if PM
 	select S5P_SLEEP if PM
 	select SAMSUNG_DMADEV
+	select ARM_ERRATA_766421
 	help
 	  Enable EXYNOS5250 SoC support

diff --git a/arch/arm/mm/proc-v7-2level.S b/arch/arm/mm/proc-v7-2level.S
index fd045e7..c663b2e 100644
--- a/arch/arm/mm/proc-v7-2level.S
+++ b/arch/arm/mm/proc-v7-2level.S
@@ -53,6 +53,8 @@  ENTRY(cpu_v7_switch_mm)
 #endif
 #ifdef CONFIG_ARM_ERRATA_754322
 	dsb
+#elif CONFIG_ARM_ERRATA_766421
+	dmb
 #endif
 	mcr	p15, 0, r1, c13, c0, 1		@ set context ID
 	isb