| Message ID | 1358701703-30919-1-git-send-email-chris@chris-wilson.co.uk (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Sun, 2013-01-20 at 17:08 +0000, Chris Wilson wrote: > During the initial bringup of IVB, we set the invalidation control to > the pre-IVB default of always invalidating TLBs on every flush: > > commit b095cd0a0ccdbc00c9fd99d90b22f8563687971f > Author: Jesse Barnes <jbarnes@virtuousgeek.org> > Date: Fri Aug 12 15:28:32 2011 -0700 > > drm/i915: set GFX_MODE to pre-Ivybridge default value even on Ivybridge > > We now have the required invalidates in place, so enable the > optimisation and avoid the unnecessary flushes when we use pipe controls > inside batches. > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Imre Deak <imre.deak@intel.com> > --- > drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c > index ae816fb..2d6d220 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -520,7 +520,7 @@ static int init_render_ring(struct intel_ring_buffer *ring) > > if (IS_GEN7(dev)) > I915_WRITE(GFX_MODE_GEN7, > - _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) | > + _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_ALWAYS) | > _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); > > if (INTEL_INFO(dev)->gen >= 5) {
On Sun, Jan 20, 2013 at 05:08:23PM +0000, Chris Wilson wrote: > During the initial bringup of IVB, we set the invalidation control to > the pre-IVB default of always invalidating TLBs on every flush: > > commit b095cd0a0ccdbc00c9fd99d90b22f8563687971f > Author: Jesse Barnes <jbarnes@virtuousgeek.org> > Date: Fri Aug 12 15:28:32 2011 -0700 > > drm/i915: set GFX_MODE to pre-Ivybridge default value even on Ivybridge > > We now have the required invalidates in place, so enable the > optimisation and avoid the unnecessary flushes when we use pipe controls > inside batches. > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> While I try to figure out how to merge this into dinq without causing too many conflicts with the patches in -fixes two bikesheds: - can we have a less confusing #define for this - the code reads as if we enable the always invalidate mode now ... - does this blow up on gen6 (docs say no), or should we try? Cheers, Daniel > --- > drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c > index ae816fb..2d6d220 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -520,7 +520,7 @@ static int init_render_ring(struct intel_ring_buffer *ring) > > if (IS_GEN7(dev)) > I915_WRITE(GFX_MODE_GEN7, > - _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) | > + _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_ALWAYS) | > _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); > > if (INTEL_INFO(dev)->gen >= 5) { > -- > 1.7.10.4 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Mon, Jan 21, 2013 at 11:38:06PM +0100, Daniel Vetter wrote: > On Sun, Jan 20, 2013 at 05:08:23PM +0000, Chris Wilson wrote: > > During the initial bringup of IVB, we set the invalidation control to > > the pre-IVB default of always invalidating TLBs on every flush: > > > > commit b095cd0a0ccdbc00c9fd99d90b22f8563687971f > > Author: Jesse Barnes <jbarnes@virtuousgeek.org> > > Date: Fri Aug 12 15:28:32 2011 -0700 > > > > drm/i915: set GFX_MODE to pre-Ivybridge default value even on Ivybridge > > > > We now have the required invalidates in place, so enable the > > optimisation and avoid the unnecessary flushes when we use pipe controls > > inside batches. > > > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > > While I try to figure out how to merge this into dinq without causing too > many conflicts with the patches in -fixes two bikesheds: > - can we have a less confusing #define for this - the code reads as if we > enable the always invalidate mode now ... Sure, but you get more conflicts that way... Taking the name from the docs, it should be GFX_TLB_INVALIDATE_MODE. > - does this blow up on gen6 (docs say no), or should we try? It is a required w/a on gen6 for the hw to modify the scanlines register, hence the previous patch. -Chris
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index ae816fb..2d6d220 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -520,7 +520,7 @@ static int init_render_ring(struct intel_ring_buffer *ring) if (IS_GEN7(dev)) I915_WRITE(GFX_MODE_GEN7, - _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) | + _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_ALWAYS) | _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); if (INTEL_INFO(dev)->gen >= 5) {
During the initial bringup of IVB, we set the invalidation control to the pre-IVB default of always invalidating TLBs on every flush: commit b095cd0a0ccdbc00c9fd99d90b22f8563687971f Author: Jesse Barnes <jbarnes@virtuousgeek.org> Date: Fri Aug 12 15:28:32 2011 -0700 drm/i915: set GFX_MODE to pre-Ivybridge default value even on Ivybridge We now have the required invalidates in place, so enable the optimisation and avoid the unnecessary flushes when we use pipe controls inside batches. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> --- drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)