iommu/intel: disable DMAR for g4x integrated gfx
diff mbox

Message ID 1358722213-2075-1-git-send-email-daniel.vetter@ffwll.ch
State New, archived
Headers show

Commit Message

Daniel Vetter Jan. 20, 2013, 10:50 p.m. UTC
DMAR support on g4x/gm45 integrated gpus seems to be totally busted.
So don't bother, but instead disable it by default to allow distros to
unconditionally enable DMAR support.

v2: Actually wire up the right quirk entry, spotted by Adam Jackson.

Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=51921
Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=538163
Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=538163
Cc: Adam Jackson <ajax@redhat.com>
Cc: David Woodhouse <dwmw2@infradead.org>
Cc: stable@vger.kernel.org
Tested-by: stathis <stathis@npcglib.org>
Tested-by: Mihai Moldovan <ionic@ionic.de>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/iommu/intel-iommu.c |   21 +++++++++++++++------
 1 file changed, 15 insertions(+), 6 deletions(-)

Comments

David Woodhouse Jan. 21, 2013, 7:03 p.m. UTC | #1
On Sun, 2013-01-20 at 23:50 +0100, Daniel Vetter wrote:
> DMAR support on g4x/gm45 integrated gpus seems to be totally busted.
> So don't bother, but instead disable it by default to allow distros to
> unconditionally enable DMAR support.

Acked-By: David Woodhouse <David.Woodhouse@intel.com>

It *really* winds me up that we never bother to test this hardware
before we ship it.

But I'm even *more* disappointed that we can't even diagnose it and
publish coherent errata *after* the fact. I'd really like to see each
quirk which disables features referencing a specific published erratum.
We really ought to be able to manage at least *that* much.

Rajesh?
Daniel Vetter Jan. 22, 2013, 10:39 p.m. UTC | #2
On Mon, Jan 21, 2013 at 01:03:48PM -0600, David Woodhouse wrote:
> On Sun, 2013-01-20 at 23:50 +0100, Daniel Vetter wrote:
> > DMAR support on g4x/gm45 integrated gpus seems to be totally busted.
> > So don't bother, but instead disable it by default to allow distros to
> > unconditionally enable DMAR support.
> 
> Acked-By: David Woodhouse <David.Woodhouse@intel.com>

Ok, I've picked that up into my drm-intel-fixes tree and will send it off
to Dave in the next few days.

> It *really* winds me up that we never bother to test this hardware
> before we ship it.
> 
> But I'm even *more* disappointed that we can't even diagnose it and
> publish coherent errata *after* the fact. I'd really like to see each
> quirk which disables features referencing a specific published erratum.
> We really ought to be able to manage at least *that* much.
> 
> Rajesh?

Yeah, some real quirk notice would be nice. I've hunted down the gen4
errata sheets, but there's nothing in there about the gfx not working for
dmar. Hence I'm opting for a working gpu in case of doubts.

Also note that according to intel docs only the gm45 and g45 have vt-d
support. So with this bug report we have them all covered. I've still left
all the other gen4 ids in the quirk tables, just in case intel marketing
materials win another round against me. Instead amended the commit message
a bit.
-Daniel

Patch
diff mbox

diff --git a/drivers/iommu/intel-iommu.c b/drivers/iommu/intel-iommu.c
index d4a4cd4..9743769 100644
--- a/drivers/iommu/intel-iommu.c
+++ b/drivers/iommu/intel-iommu.c
@@ -4196,6 +4196,21 @@  static struct iommu_ops intel_iommu_ops = {
 	.pgsize_bitmap	= INTEL_IOMMU_PGSIZES,
 };
 
+static void __devinit quirk_iommu_g4x_gfx(struct pci_dev *dev)
+{
+	/* G4x/GM45 integrated gfx dmar support is totally busted. */
+	printk(KERN_INFO "DMAR: Disabling IOMMU for graphics on this chipset\n");
+	dmar_map_gfx = 0;
+}
+
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_g4x_gfx);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e00, quirk_iommu_g4x_gfx);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e10, quirk_iommu_g4x_gfx);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e20, quirk_iommu_g4x_gfx);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e30, quirk_iommu_g4x_gfx);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e40, quirk_iommu_g4x_gfx);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e90, quirk_iommu_g4x_gfx);
+
 static void __devinit quirk_iommu_rwbf(struct pci_dev *dev)
 {
 	/*
@@ -4204,12 +4219,6 @@  static void __devinit quirk_iommu_rwbf(struct pci_dev *dev)
 	 */
 	printk(KERN_INFO "DMAR: Forcing write-buffer flush capability\n");
 	rwbf_quirk = 1;
-
-	/* https://bugzilla.redhat.com/show_bug.cgi?id=538163 */
-	if (dev->revision == 0x07) {
-		printk(KERN_INFO "DMAR: Disabling IOMMU for graphics on this chipset\n");
-		dmar_map_gfx = 0;
-	}
 }
 
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_rwbf);