intel/iommu: force writebuffer-flush quirk on Gen 4 Chipsets
diff mbox

Message ID 1358794139-4820-1-git-send-email-daniel.vetter@ffwll.ch
State New, archived
Headers show

Commit Message

Daniel Vetter Jan. 21, 2013, 6:48 p.m. UTC
We already have the quirk entry for the mobile platform, but also
reports on some desktop versions. So be paranoid and set it
everywhere.

References: http://www.mail-archive.com/dri-devel@lists.freedesktop.org/msg33138.html
Cc: stable@vger.kernel.org
Cc: David Woodhouse <dwmw2@infradead.org>
Reported-and-tested-by: Mihai Moldovan <ionic@ionic.de>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/iommu/intel-iommu.c |    8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

Comments

David Woodhouse Jan. 22, 2013, 6:55 p.m. UTC | #1
On Mon, 2013-01-21 at 19:48 +0100, Daniel Vetter wrote:
> We already have the quirk entry for the mobile platform, but also
> reports on some desktop versions. So be paranoid and set it
> everywhere.
> 
> References: http://www.mail-archive.com/dri-devel@lists.freedesktop.org/msg33138.html
> Cc: stable@vger.kernel.org
> Cc: David Woodhouse <dwmw2@infradead.org>
> Reported-and-tested-by: Mihai Moldovan <ionic@ionic.de>
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
>  drivers/iommu/intel-iommu.c |    8 +++++++-
>  1 file changed, 7 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/iommu/intel-iommu.c b/drivers/iommu/intel-iommu.c
> index 9743769..19854bf 100644
> --- a/drivers/iommu/intel-iommu.c
> +++ b/drivers/iommu/intel-iommu.c
> @@ -4215,13 +4215,19 @@ static void __devinit quirk_iommu_rwbf(struct pci_dev *dev)
>  {
>  	/*
>  	 * Mobile 4 Series Chipset neglects to set RWBF capability,
> -	 * but needs it:
> +	 * but needs it. Same seems to hold for the desktop versions.
>  	 */
>  	printk(KERN_INFO "DMAR: Forcing write-buffer flush capability\n");
>  	rwbf_quirk = 1;
>  }
>  
>  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_rwbf);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e00, quirk_iommu_rwbf);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e10, quirk_iommu_rwbf);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e20, quirk_iommu_rwbf);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e30, quirk_iommu_rwbf);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e40, quirk_iommu_rwbf);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e90, quirk_iommu_rwbf);
>  
>  #define GGC 0x52
>  #define GGC_MEMORY_SIZE_MASK	(0xf << 8)

Again, I'm really unhappy about doing this kind of thing based on
hearsay. This should have a specific reference (with URL) to a published
erratum. Rajesh?
Daniel Vetter Feb. 13, 2013, 6:40 p.m. UTC | #2
On Tue, Jan 22, 2013 at 7:55 PM, David Woodhouse <dwmw2@infradead.org> wrote:
> On Mon, 2013-01-21 at 19:48 +0100, Daniel Vetter wrote:
>> We already have the quirk entry for the mobile platform, but also
>> reports on some desktop versions. So be paranoid and set it
>> everywhere.
>>
>> References: http://www.mail-archive.com/dri-devel@lists.freedesktop.org/msg33138.html
>> Cc: stable@vger.kernel.org
>> Cc: David Woodhouse <dwmw2@infradead.org>
>> Reported-and-tested-by: Mihai Moldovan <ionic@ionic.de>
>> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
>> ---
>>  drivers/iommu/intel-iommu.c |    8 +++++++-
>>  1 file changed, 7 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/iommu/intel-iommu.c b/drivers/iommu/intel-iommu.c
>> index 9743769..19854bf 100644
>> --- a/drivers/iommu/intel-iommu.c
>> +++ b/drivers/iommu/intel-iommu.c
>> @@ -4215,13 +4215,19 @@ static void __devinit quirk_iommu_rwbf(struct pci_dev *dev)
>>  {
>>       /*
>>        * Mobile 4 Series Chipset neglects to set RWBF capability,
>> -      * but needs it:
>> +      * but needs it. Same seems to hold for the desktop versions.
>>        */
>>       printk(KERN_INFO "DMAR: Forcing write-buffer flush capability\n");
>>       rwbf_quirk = 1;
>>  }
>>
>>  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_rwbf);
>> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e00, quirk_iommu_rwbf);
>> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e10, quirk_iommu_rwbf);
>> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e20, quirk_iommu_rwbf);
>> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e30, quirk_iommu_rwbf);
>> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e40, quirk_iommu_rwbf);
>> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e90, quirk_iommu_rwbf);
>>
>>  #define GGC 0x52
>>  #define GGC_MEMORY_SIZE_MASK (0xf << 8)
>
> Again, I'm really unhappy about doing this kind of thing based on
> hearsay. This should have a specific reference (with URL) to a published
> erratum. Rajesh?

Any updates here? I'd like to include this for 3.9 -next with cc:
stable to finally allow distros to enable DMAR/IOMMU support by
default on Intel hw. The current state of affairs is simply
embarrassing imo :(
-Daniel
Daniel Vetter Feb. 18, 2013, 3:12 p.m. UTC | #3
On Wed, Feb 13, 2013 at 07:40:05PM +0100, Daniel Vetter wrote:
> On Tue, Jan 22, 2013 at 7:55 PM, David Woodhouse <dwmw2@infradead.org> wrote:
> > On Mon, 2013-01-21 at 19:48 +0100, Daniel Vetter wrote:
> >> We already have the quirk entry for the mobile platform, but also
> >> reports on some desktop versions. So be paranoid and set it
> >> everywhere.
> >>
> >> References: http://www.mail-archive.com/dri-devel@lists.freedesktop.org/msg33138.html
> >> Cc: stable@vger.kernel.org
> >> Cc: David Woodhouse <dwmw2@infradead.org>
> >> Reported-and-tested-by: Mihai Moldovan <ionic@ionic.de>
> >> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> >> ---
> >>  drivers/iommu/intel-iommu.c |    8 +++++++-
> >>  1 file changed, 7 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/drivers/iommu/intel-iommu.c b/drivers/iommu/intel-iommu.c
> >> index 9743769..19854bf 100644
> >> --- a/drivers/iommu/intel-iommu.c
> >> +++ b/drivers/iommu/intel-iommu.c
> >> @@ -4215,13 +4215,19 @@ static void __devinit quirk_iommu_rwbf(struct pci_dev *dev)
> >>  {
> >>       /*
> >>        * Mobile 4 Series Chipset neglects to set RWBF capability,
> >> -      * but needs it:
> >> +      * but needs it. Same seems to hold for the desktop versions.
> >>        */
> >>       printk(KERN_INFO "DMAR: Forcing write-buffer flush capability\n");
> >>       rwbf_quirk = 1;
> >>  }
> >>
> >>  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_rwbf);
> >> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e00, quirk_iommu_rwbf);
> >> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e10, quirk_iommu_rwbf);
> >> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e20, quirk_iommu_rwbf);
> >> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e30, quirk_iommu_rwbf);
> >> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e40, quirk_iommu_rwbf);
> >> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e90, quirk_iommu_rwbf);
> >>
> >>  #define GGC 0x52
> >>  #define GGC_MEMORY_SIZE_MASK (0xf << 8)
> >
> > Again, I'm really unhappy about doing this kind of thing based on
> > hearsay. This should have a specific reference (with URL) to a published
> > erratum. Rajesh?
> 
> Any updates here? I'd like to include this for 3.9 -next with cc:
> stable to finally allow distros to enable DMAR/IOMMU support by
> default on Intel hw. The current state of affairs is simply
> embarrassing imo :(

Whatever, I want to get this off my table, so merged to drm-intel-fixes
for 3.9.
-Daniel

Patch
diff mbox

diff --git a/drivers/iommu/intel-iommu.c b/drivers/iommu/intel-iommu.c
index 9743769..19854bf 100644
--- a/drivers/iommu/intel-iommu.c
+++ b/drivers/iommu/intel-iommu.c
@@ -4215,13 +4215,19 @@  static void __devinit quirk_iommu_rwbf(struct pci_dev *dev)
 {
 	/*
 	 * Mobile 4 Series Chipset neglects to set RWBF capability,
-	 * but needs it:
+	 * but needs it. Same seems to hold for the desktop versions.
 	 */
 	printk(KERN_INFO "DMAR: Forcing write-buffer flush capability\n");
 	rwbf_quirk = 1;
 }
 
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_rwbf);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e00, quirk_iommu_rwbf);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e10, quirk_iommu_rwbf);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e20, quirk_iommu_rwbf);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e30, quirk_iommu_rwbf);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e40, quirk_iommu_rwbf);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e90, quirk_iommu_rwbf);
 
 #define GGC 0x52
 #define GGC_MEMORY_SIZE_MASK	(0xf << 8)